US 6,275,970 B1 · Evaluation of the design quality of network nodes

Abstract

A method and apparatus for detecting a predischarge node in an integrated circuit. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a predischarge node exists in the integrated circuit. The rules checker program evaluates each node in the integrated circuit and determines whether or not an N field effect transistor (NFET) is connected to the node and, if so, whether the gate terminal of the NFET is connected to a clock and whether a drain or source terminal of the NFET is connected to ground. The rules checker program also determines whether or not a P field effect transistor (PFET) is connected to the node being evaluated and, if so, whether it has a gate terminal which is not connected to a clock and drain and source terminals which are not connected to a supply. If all of these conditions are true, the rules checker program determines that the node being evaluated is a predischarge node.

Claims13

Dependent claims

An apparatus for detecting a predischarge node in an integrated circuit, the apparatus comprising:

a computer capable of being configured to execute a rules checker program, the rules checker program analyzing information relating to the integrated circuit to determine whether a predischarge node exists in the integrated circuit, wherein when the rules checker program is executed by the computer, the rules checker program evaluates each node in the integrated circuit to determine whether or not each node in the circuit is a predischarge node by analyzing the information relating to the integrated circuit to determine whether or not the node being evaluated is connected to an N field effect transistor and to a P field effect transistor, by determining whether or not the N field effect transistor has a gate terminal which is connected to a clock and has either a drain or a source terminal connected to ground, and by determining whether or not the P field effect transistor has a gate terminal which is not connected to a clock and has drain and source terminals which are not connected to a supply.

A computer program embodied on a computer-readable medium, the computer program evaluating nodes of a circuit design to determine whether or not any of the nodes are predischarge nodes, the program comprising:

a first code segment for determining whether an N field effect transistor of the circuit design has a gate terminal connected to a clock and a drain or source terminal connected to ground;
and
a second code segment for determining whether a P field effect transistor of the circuit design has a gate terminal which is not connected to a clock and drain and source terminals which are not connected to a supply.

Dependencies are inferred from the claim text.

Evaluation of the design quality of network nodes

Life of this patent

Evaluation of the design quality of network nodes

Life of this patent

Abstract

Claims13