Test circuit and a redundancy circuit for an internal memory circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHideshi Maeno, Tokuya {overscore (O)}sawa
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Abstract
In the first test mode with a shift-mode signal (SM) of “1” and a test-mode signal (TM) of “1”, supplying a comparison control signal (CMP) of “1” makes a test-valid condition. Then, a comparison result between input data (D) which becomes “0” to indicate a failure and an expected value data (EXP) (an output of a comparator (21)) and an AND-operation result between a serial input (SI) and a latch data (an output of a D-FF (27)) are given to the D-FF (27) through NAND gates (28 and 29), an AND gate (30) and a selector (26). With this configuration achieved is a semiconductor integrated circuit having a test circuit which allows a quick recognition of whether there is a failure or not in an internal memory circuit under test.
Claims20
A semiconductor integrated circuit device, comprising:
- a memory circuit under test which can output in parallel a plurality of output data corresponding to a plurality of bits based on an internally-stored content;
- and
- a test circuit having a plurality of scan flip flops (S-FFs) provided correspondingly to said plurality of output data, said plurality of S-FFs receiving serial output data of their respective preceding S-FFs as serial input data to be connected in series to one another,
- each of said plurality of S-FFs comprising:
- a comparison circuit for comparing at least one of said plurality of output data with at least one of expected value data corresponding thereto to output a comparison result data indicating whether there is a failure or not;
- and
- failure-information transfer means receiving a group of failure judging data including said comparison result data in a first test mode, for outputting said serial output data indicating a failure when at least one data of said group of failure judging data indicate a failure, and
- said group of failure judging data of said failure-information transfer means in each of one or more serial S-FFs among said plurality of S-FFs further including said serial input data in addition to said comparison result data.
Dependencies are inferred from the claim text.