Circuit and method for performing tests on memory array cells using external sense amplifier reference current

An integrated memory circuit operable in a selected one of a test mode and a normal operating mode, the circuit comprising:

• a memory array including rows and columns of memory cells;
• a sense amplifier having a first input for connection to a selected one of the columns and a reference input connected to a first node;
• a first external pad to which a first external voltage is applied;
• a first test mode circuit, coupled to the sense amplifier and to the first external pad, and configured during the test mode to apply a test voltage that depends on the first external voltage to the reference input of the sense amplifier and to connect the first input of the sense amplifier to the selected one of the columns;
• a second external pad to which a second external voltage is applied;
• and
• a second test mode circuit, coupled to the second external pad and to the memory array, and configured during the test mode to apply the second external voltage to the memory array.

An integrated memory circuit, comprising:

• an array of memory cells;
• a sense amplifier having a reference input, wherein the sense amplifier is coupled to the array for sensing and amplifying data stored by the memory cells;
• a first external pad to which a first external voltage is applied;
• a first switch circuit for selectively coupling the first external voltage to the reference input of the sense amplifier during a test mode of operation;
• a second external pad to which a second external voltage is applied;
• and
• a second switch circuit for selectively coupling the second external voltage to the array of memory cells during the test mode of operation.

An integrated memory circuit, comprising:

• an array of memory cells;
• a sense amplifier having a reference input, and a sensing input coupled to the array;
• a first external input/output connection, selectively coupled to the reference input, for receiving an externally-provided reference signal, the sense amplifier using the externally-provided reference signal in lieu of an internal reference signal during a test operation;
• and
• a second external input/output connection, selectively coupled to the array, for receiving an externally-provided supply voltage, the array using the externally-provided supply voltage in lieu of an internal supply voltage during the test operation.

A method of operating an integrated memory circuit, the circuit including a memory array including rows and columns of memory cells, a sense amplifier having a sensing input coupled to the array and a reference input, and first and second external pads, comprising:

• initiating a testing mode of operation;
• during the testing mode, applying a test signal to the reference input of the sense amplifier, the test signal depending on an external test signal received from the first external pad;
• during the testing mode, connecting the sensing input of the sense amplifier to the array;
• and
• during the testing mode, applying an external supply voltage to the memory array, the external supply voltage received from the second external pad.

A method of operating an integrated memory circuit, comprising:

• initiating a testing mode of operation;
• receiving a first external voltage from a first external pad;
• coupling the first external voltage to a reference input of a sense amplifier during the testing mode;
• receiving a second external voltage from a second external pad;
• and
• coupling the second external voltage to an array of memory cells during the testing mode.

A method of testing an integrated memory circuit, comprising:

• initiating a testing mode;
• during the testing mode, decoupling an internal reference signal from a reference input of a sense amplifier, and coupling an external reference signal to the reference input of the sense amplifier, the external reference signal received from a first external input/output connection;
• and
• during the testing mode, decoupling an internal supply voltage from an array of memory cells, and coupling an external supply voltage to the array of memory cells, the external supply voltage received from a second external input/output connection.