Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof

A method of self-test and correction of errors due to a loss charge for a flash memory comprising an array of cells organized in rows and columns, and being erasable and programmable by whole sectors in which the array is divided, the flash memory comprising at least one additional row and at least one additional column of cells for each memory sector, the method comprising the steps of:

• storing parity codes in the additional at least one row and in the additional at least one column, respectively, by
• reading in sequence all bytes of a first row of a sector, counting the number of “1”s in the first row, verifying a parity, and programming a respective parity bit in the additional at least one column, and repeating the reading, counting, verifying and programming operations by incrementing a row address until executing the operations for a last row of the sector, and
• reading in sequence all bytes of a first column of the sector, counting the number of “1”s in the first column, verifying a parity, and programming a respective parity bit in the additional at least one row and repeating the reading, counting, verifying and programming operations by incrementing a column address until executing the operations for a last column of the sector;
• and
• carrying out periodically a self-test routine and eventual correction routine comprising the following steps
• repeating the reading in sequence per bytes and parity check,
• verifying parity consistency of the parity check value with the respective stored parity bit,
• if the verifying parity consistency is negative, retaining a current row address and proceeding to sequentially verify column parity starting from the first column until identifying a column for which verification yields a negative result thereby identifying a failed bit, and
• if the failed bit is “1” reprogramming it to “0”.

A method operating a flash memory comprising an array of cells organized in rows and columns, and being erasable and programmable by whole sectors in which the array is divided, the flash memory comprising at least one additional row and at least one additional column of cells for each memory sector, the method comprising the steps of:

• performing a self-test and correction of errors due to a loss charge for the flash memory automatically during a power-on routine of a system employing the flash memory, the self-test and correction comprising the steps of
• storing parity codes in the additional at least one row and in the additional at least one column, respectively, by
• reading in sequence all bytes of a first row of a sector, counting the number of “1”s in the first row, verifying a parity, and programming a respective parity bit in the additional at least one column, and repeating the reading, counting, verifying and programming operations by incrementing a row address until executing the operations for a last row of the sector, and
• reading in sequence all bytes of a first column of the sector, counting the number of “1”s in the first column, verifying a parity, and programming a respective parity bit in the additional at least one row and repeating the reading, counting, verifying and programming operations by incrementing a column address until executing the operations for a last column of the sector;
• and
• carrying out periodically a self-test routine and eventual correction routine comprising the following steps
• repeating the reading in sequence per bytes and parity check,
• verifying parity consistency of the parity check value with the respective stored parity bit,
• if the verifying parity consistency is negative, retaining a current row address and proceeding to sequentially verify column parity starting from the first column until identifying a column for which verification yields a negative result thereby identifying a failed bit, and
• if the failed bit is “1” reprogramming it to “0”.

A method operating a flash memory comprising an array of cells organized in rows and columns, and being erasable and programmable by whole sectors in which the array is divided, the flash memory comprising at least one additional row and at least one additional column of cells for each memory sector, the method comprising the steps of:

• performing a self-test and correction of errors due to a loss charge for the flash memory responsive to a command, the self-test and correction comprising the steps of
• storing parity codes in the additional at least one row and in the additional at least one column, respectively, by
• reading in sequence all bytes of a first row of a sector, counting the number of “1”s in the first row, verifying a parity, and programming a respective parity bit in the additional at least one column, and repeating the reading, counting, verifying and programming operations by incrementing a row address until executing the operations for a last row of the sector, and
• reading in sequence all bytes of a first column of the sector, counting the number of “1”s in the first column, verifying a parity, and programming a respective parity bit in the additional at least one row and repeating the reading, counting, verifying and programming operations by incrementing a column address until executing the operations for a last column of the sector;
• and
• carrying out periodically a self-test routine and eventual correction routine comprising the following steps
• repeating the reading in sequence per bytes and parity check,
• verifying parity consistency of the parity check value with the respective stored parity bit,
• if the verifying parity consistency is negative, retaining a current row address and proceeding to sequentially verify column parity starting from the first column until identifying a column for which verification yields a negative result thereby identifying a failed bit, and
• if the failed bit is “1” reprogramming it to “0”.

A system comprising:

• a flash memory being erasable and programmable by whole sectors, said flash memory comprising an array of NOR cells organized in rows and columns;
• each sector comprising at least one additional column and at least one additional row in which to store parity codes relative to parity checks of bytes of each row and parity checks of bytes of each column, respectively, allowing for periodic self-testing checks and correction of eventual loss of charge error of at least one cell per sector;
• and
• said flash memory being responsive to a set of instructions for performing the self-test and correction by storing parity codes in the at least one additional row and in the at least one additional column, respectively, by
• reading in sequence all bytes of a first row of a sector, counting the number of “1”s in the first row, verifying a parity, and programming a respective parity bit in the at least one additional column, and repeating the reading, counting, verifying and programming operations by incrementing a row address until executing the operations for a last row of the sector, and
• reading in sequence all bytes of a first column of the sector, counting the number of “1”s in the first column, verifying a parity, and programming a respective parity bit in the at least one additional row and repeating the reading, counting, verifying and programming operations by incrementing a column address until executing the operations for a last column of the sector, and
• carrying out periodically a self-test routine and eventual correction routine comprising
• repeating the reading in sequence per bytes and parity check,
• verifying parity consistency of the parity check value with the respective stored parity bit,
• if the verifying parity consistency is negative, retaining a current row address and proceeding to sequentially verify column parity starting from the first column until identifying a column for which verification yields a negative result thereby identifying a failed bit, and if the failed bit is “1” reprogramming it to “0”.