Reset signal control circuit of a one-chip microcomputer

Abstract

This invention provides a reset signal control circuit of one-chip microcomputer including an interrupt signal which requires to stop temporarily a currently progressing operation and to perform a predetermined other operation; a clock oscillator which is enabled by an activated interrupt signal and generates clock signals with desired frequencies and widths according to an oscillation operation of an external oscillation means; a detection means which detects the frequencies and widths of the clock signals and produces the desired detected signals according to the detected values; a comparator which produces activated reset signals when enabled by the activated interrupt signal, compares a reference signal and a serial voltage, and maintains an activated state of the reset signal if the serial voltage is lower than the reference voltage and inactivates the reset signal if the serial voltage is higher than the reference voltage, offering effects to reduce the area occupied in the chip by constituting the reset signal control circuit using a rectifier and a comparator which occupies relatively small layout area and to reduce the test time by optimizing the time at which the operation of the exterior oscillation means is stabilized and an activating time of the interior reset signal.

Dependencies are inferred from the claim text.