Microprocessor instruction pipeline having inhibit logic at each stage
AssigneeCSEM Centre Suisse d'Electronique et de Microtechnique SA
InventorsClaude Arm, Jean-Marc Masgonty, Christian Piguet
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Abstract
The disclosure relates to microprocessors and, more particularly, to a system for organizing and a method for the sequencing of the circuits of a microprocessor. The instruction registers are connected in chains and an inhibiting device is associated with each instruction register. Each inhibiting device has its inputs connected to the inputs of the associated register and to the clock circuit a provides and signal for the loading of the associated instruction register when it detects a predetermined combination of digits in the associated register.
Claims5
A microprocessor instruction pipeline having interconnected instruction register stages, the microprocessor comprising:
- addressable program memory means for providing instructions at its output;
- a plurality of instruction registers forming pipeline stages, each register having an instruction input and a clock input;
- means for connecting an instruction output from an instruction register of each stage to an instruction input of an instruction register of a succeeding stage, the loading of instructions between stages being enabled by a clock signal applied to the clock input of a receiving register;
- and
- a separate inhibit means located at each stage for enabling a clock applied to the clock input of a correspondingly connected instruction register in response to decoding of the instruction contained in the instruction register of a preceding stage.
Dependencies are inferred from the claim text.