System and method for writing back multiple results over a single-result bus and processor employing the same
AssigneeVIA-Cyrix, Inc.
InventorNicholas G. Samra
Life of this patent
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Abstract
For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for, and method of, writing back the results of the multiple-result instruction. In one embodiment, the system includes: (1) multi-result node creation circuitry that creates a multi-result node having at least first and second results for the multiple-result instruction and (2) node transmission circuitry, coupled to the multi-result node creation circuitry, that transmits the first and second results of said multi-result node sequentially over the result bus.
Claims28
For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for writing back said results of said multiple-result instruction, comprising:
- multi-result node creation circuitry that creates a multi-result node having at least first and second results for said multiple-result instruction;
- and
- node transmission circuitry, coupled to said multi-result node creation circuitry, that transmits said first and second results of said multi-result node sequentially over said result bus.
For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for writing back said results of said multiple-result instruction, comprising:
- means for creating a multi-result node having at least first and second results for said multiple-result instruction;
- and
- means, coupled to said means for creating, for transmitting said first and second results of said multi-result node sequentially over said result bus.
For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a method of writing back said results of said multiple-result instruction, comprising:
- creating a multi-result node having at least first and second results for said multiple-result instruction;
- and
- transmitting said first and second results of said multi-result node sequentially over said result bus.
A computer system, comprising:
- (a) a processor having an integer execution core containing at least two execution result buses for executing instructions and of insufficient width to convey all results of a given multiple-result instruction concurrently, said processor capable of addressing segments of system memory coupled thereto;
- (b) system memory for storing instructions;
- (c) said processor including decode units for decoding an ordered stream of instructions fetched from said system memory;
- and
- (d) a system for writing back said results of said multiple-result instruction, including:
- (i) multi-result node creation circuitry that creates a multi-result node having at least first and second results for said multiple-result instruction, and
- (ii) node transmission circuitry, coupled to said multi-result node creation circuitry, that transmits said first and second results of said multi-result node sequentially over said result bus.
Dependencies are inferred from the claim text.