System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time

A method of buffering instructions in a processor having an instruction buffer, the method comprising the steps of:

• buffering at least two instructions in the instruction buffer equal to the number of stages in the processor before the decode stage;
• detecting that the instruction buffer cannot receive any additional instructions;
• in response to detecting that the instruction buffer cannot receive any additional instructions, reissuing a previous fetch for an instruction in a memory until the instruction buffer is no longer full;
• and
• writing the fetched instruction into the instruction buffer after the instruction buffer is no longer full.

A processor pipeline comprising:

• a plurality of sequential stages followed by a decode stage;
• a limited instruction buffer operable to concurrently store a number of instructions the number being at least two and [less than or] equal to the number of sequential stages, and no more;
• a counter system, the counter system including a counter for storing a count designating an address of a memory location that stores an instruction for receipt by the limited instruction buffer, the counter system operable to adjust the count of the counter based on a status of the decode stage;
• and
• the plurality of sequential stages comprising a fetch unit operable to fetch the instruction at the address designated by the count.