Data processing device to compress and decompress VLIW instructions by selectively storing non-branch NOP instructions

A data processing device with an instruction compression function and an instruction decompression function for VLIW instructions, comprising:

• an instruction storage memory to store at least specific instruction code strings for controlling a computer in a compressed form with compression information indicating a form of compression, and to selectively store non-branch NOP instructions;
• an instruction buffer to store decompressed instructions;
• an auxiliary buffer to temporarily store part of an instruction being decompressed;
• a first switch to selectively input instruction code strings of high-order slots read from said instruction storage memory into said instruction buffer;
• a second switch to selectively input instruction code strings of low-order slots read from said instruction storage memory into said instruction buffer and said auxiliary buffer;
• a third switch to transfer contents of said auxiliary buffer to said instruction buffer;
• and
• a control circuit to control the first, second, and third switch according to the compression information,
• wherein the attached compression information indicates whether a succeeding VLIW instruction is filled with NOP instructions.

A data processing device with an instruction compression function and an instruction decompression function for VLIW instructions, comprising:

• an instruction storage memory to read or write instruction codes for controlling a computer in units of instruction code strings including a predetermined number of instruction codes in a compressed form and storage position information attached to each instruction code by deleting specific instruction codes;
• and
• an instruction code decompression circuit to decompress each instruction code according to the attached storage position information,
• wherein NOP instructions are left in a compressed code string such that consecutively deleted NOP instructions will not exceed the predetermined number in a compression code string when NOP instructions are deleted from an NOP instruction string in an instruction code string before compression.

A data processing device with an instruction compression function and an instruction decompression function for VLIW instructions, comprising:

• an instruction storage memory to read or write instruction codes for controlling a computer in units of instruction code strings, each instruction code string including a specified number of instruction codes in a compressed form and storage position information attached to each instruction code by deleting specific instruction codes, said instruction storage memory selectively storing non-branch NOP instructions;
• a plurality of instructions buffers to store a plurality of instruction codes and to cyclically fetch a plurality of instructions;
• an instruction code distribution unit to develop a compressed instruction code string read from said instruction storage memory and send the instruction codes to respective instruction buffers of said plurality of instruction buffers;
• and
• a control circuit to control the development of a compressed instruction code string in said instruction distribution unit according to storage position information attached to each instruction code and instruction buffer information indicating an instruction buffer from which an instruction is output,
• wherein NOP instructions are left in a compressed code string such that consecutively deleted NOP instructions will not exceed the predetermined number in a compression code string when NOP instructions are deleted from an NOP instruction string in an instruction code string before compression.

A data processing device with an instruction compression function and an instruction decompression function, comprising:

• an instruction storage memory to store specific instruction code strings for controlling a computer in a compressed form with attached compression information indicating a form of compression;
• and
• an instruction code decompression circuit to restore a code string read from said instruction storage memory to an original status according to the attached compression information,
• wherein a program counter is not added to an instruction code deleted for compression and a program counter is added to an instruction code stored in said instruction storage memory,
• wherein the attached compression information indicates whether a succeeding VLIW instruction is filled with NOP instructions, and wherein non-branch NOP instructions are selectively stored in said instruction storage memory.

A data processing device with an instruction compression function and an instruction decompression function for VLIW instructions, comprising:

• an instruction storage memory to read or write units of instruction code strings for controlling a computer including a predetermined number of instruction codes in a compressed form with storage position information attached to each instruction code by deleting specific instruction codes;
• and
• an instruction code decompression circuit to decompress each instruction code according to the attached storage position information,
• wherein a program counter is not added to an instruction code deleted for compression, and a program counter is added to an instruction code stored in said instruction storage memory,
• wherein NOP instructions are left in a compressed code string such that consecutively deleted NOP instructions will not exceed the predetermined number in a compression code string when NOP instructions are deleted from an NOP instruction string in an instruction code string before compression.

A data processing device with an instruction compression function and an instruction decompression function for VLIW instructions, comprising:

• an instruction storage memory to store specific instruction code strings for controlling a computer in a compressed form, wherein each instruction code string includes attached compression information indicating a form of compression, and to selectively store non-branch NOP instructions;
• and
• an instruction code decompression circuit to decompress a compressed instruction code string read from said instruction storage memory according to the attached compression information,
• wherein succeeding instruction information indicating that a succeeding VLIW instruction includes only NOP instructions is added to the compression information of the instruction code string, thereby storing information from the succeeding instruction code string in said instruction storage memory without storing the succeeding VLIW instruction.