US 6,275,920 B1 · Mesh connected computed

Abstract

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. “Hit” detection and histogram logic are also included.

Claims48

Dependent claims

An apparatus for processing data, comprising:

at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes a random access memory (RAM) having a plurality of storage locations, and wherein each storage location is capable of storing an n-bit data unit, n being an integer greater than zero;
and
a controller for generating processing element command words that are supplied to the at least one processing element and which cause the at least one processing element to manipulate an M-bit operand, M being evenly divisible by n,
wherein:
the controller utilizes an image descriptor that represents the M-bit operand to generate addresses for accessing the M-bits of the operand stored in the RAM;
and
the image descriptor includes a map field comprising a plurality of address fields, each for addressing one of the storage locations in the RAM.

4 more elements

An apparatus for processing data, comprising:

at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes a first random access memory (RAM) having a plurality of storage locations, and a second RAM having a plurality of storage locations, and wherein each storage location is capable of storing an n-bit data unit, n being an integer greater than zero;
and
a controller for generating processing element command words that are supplied to the at least one processing element and which cause the at least one processing element to manipulate an operand stored in one of the first and second RAMs,
wherein:
the controller utilizes an image descriptor that represents the operand to generate memory controls and addresses for accessing the operand stored in said one of the first and second RAMs;
and
the image descriptor includes a storage field for indicating in which of the first and second RAMs the operand is stored.

4 more elements

A method of operating a data processing apparatus comprising at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes a first random access memory (RAM) having a plurality of storage locations, and a second RAM having a plurality of storage locations, and wherein each storage location is capable of storing an n-bit data unit, n being an integer greater than zero;

and a controller for generating processing element command words that are supplied to the at least one processing element and which cause the at least one processing element to manipulate an operand stored in one of the first and second RAMs, the method comprising the steps of:
in the controller:
utilizing an image descriptor that represents the operand to generate memory controls and addresses for accessing the operand stored in said one of the first and second RAM,
wherein the image descriptor includes a storage field for indicating in which of the first and second RAMs the operand is stored.

1 more element

Dependencies are inferred from the claim text.

Mesh connected computed

Life of this patent

Mesh connected computed

Life of this patent

Abstract

Claims48