High-speed address translation system
AssigneeFujitsu Limited
InventorTakashi Okada
Life of this patent
Estimating the term…
Abstract
In a high-speed address translation system provided in a computer system including a logical address space storing logical addresses, a physical address space for storing physical addresses and a microprocessor unit connected to both address spaces, and the microprocessor unit including a memory management unit (MMU), the system according to the present invention includes; a TLB provided in the MMU for translating the logical address to the physical address; and a unit for adjusting a size of each section formed of a file to a predetermined page size in an offline process in accordance with memory allocation designed in the offline process.
Claims6
A high-speed address translation system provided in a computer system including a logical address space storing logical addresses, a physical address space for storing physical addresses and a microprocessor unit connected to both address spaces, and the microprocessor unit including a memory management unit, the system comprising:
- a translation lookaside buffer (TLB) provided in the memory management unit for translating the logical address to the physical address;
- and
- means for adjusting a size of sections formed of a file to a predetermined page size in an offline process in accordance with memory allocation designed in the offline process,
- wherein the predetermined page size is a large page size and, when a sum of the size of each section does not reach to the large page size and a fractional page size occurs, a dummy section is provided to the size of the fraction in the offline process, and the dummy section is merged with each section forming the large page size so that whether or not the page size is large is easily determined at high speed in an online program, and
- wherein an interface is provided to the memory management unit in order to allocate the memory which becomes the large page size, for a program which performs memory allocation in an online process, and
- wherein, the online process is executed by an online program module which is formed of sections including user code, user data, privileged code and privileged data, and
- wherein an offline program module is translated into the online program module, in the above translation, both user codes in the offline program module are merged to one user code in the online program module, both user data are merged to one user data, both privileged codes are merged to one privileged code, and both privileged data are merged to one privileged data.
A high-speed address translation system provided in a computer system including a logical address space storing logical addresses, a physical address space for storing physical addresses and a microprocessor unit connected to both address spaces, and the microprocessor unit including a memory management unit, the system comprising:
- a translation lookaside buffer (TLB) provided in the memory management unit for translating the logical address to the physical address;
- and
- means for adjusting a size of sections formed of a file to a predetermined page size in an offline process in accordance with memory allocation designed in the offline process, wherein, the offline process is executed by an offline program module which is formed of at least two user programs each including user code and user data, and at least two privileged programs each including privileged code and privileged data, and
- wherein the offline program module is translated into the online program module, in the above translation, both user codes in the offline program module are merged to one user code in the online program module, both user data are merged to one user data, both privileged codes are merged to one privileged code, and both privileged data are merged to one privileged data.
Dependencies are inferred from the claim text.