Cache coherency protocol including an HR state

A method of maintaining cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said method comprising:

• in a first cache among said plurality of caches, storing a first data item in association with an address tag indicating an address of said first data item and setting a coherency indicator in said first cache to a first state that indicates that said address tag is valid and that said first data item is invalid in said first cache;
• if, while said coherency indicator is set to said first state, said first cache detects a data transfer on said interconnect associated with said address indicated by said address tag, said data transfer being initiated by another of said plurality of caches and including a second data item that is modified with respect to a corresponding data item in said system memory, storing said second data item in said first cache in association with said address tag and updating said coherency indicator to a second state indicating that said second data item is valid and that said first cache, among all of said plurality of caches, is responsible for supplying said second data item in response to a request;
• and
• writing said second data item from said first cache to said system memory in response to deallocation by said first cache of a cache line containing said second data item.

A cache for supporting cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said cache comprising:

• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, wherein said first state indicates that said address tag is valid and that said first data item is invalid;
• and
• a cache controller that, responsive to detection of a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, wherein said data transfer is initiated by another of said plurality of caches and not requested by said first cache and includes a second data item that is modified with respect to a corresponding data item in said system memory, stores said second data item in said cache in association with said address tag and updates said coherency indicator to a second state indicating that said second data item is valid in said cache and that said cache, of all of said plurality of caches, is responsible for supplying said second data item in response to a request.

A cache for supporting cache coherency in a data processing system including a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect, said cache comprising:

• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, wherein said first state indicates that said address tag is valid and that said first data item is invalid;
• a cache controller that, responsive to detection of a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, wherein said data transfer is initiated by another of said plurality of caches and includes a second data item that is modified with respect to a corresponding data item in said system memory, stores said second data item in said cache in association with said address tag and updates said coherency indicator to a second state indicating that said second data item is valid and that said cache, of all of said plurality of caches, is responsible for supplying said second data item in response to a request;
• and
• wherein said cache controller includes means for writing said second data item from said cache to said system memory responsive to deallocation by said cache of a cache line containing said second data item.

A data processing system, comprising:

• an interconnect;
• a plurality of processors;
• a plurality of caches coupled to said plurality of processor and to said interconnect, wherein a first cache among said plurality of caches includes:
• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, wherein said first state indicates that said address tag is valid and that said first data item is invalid;
• and
• a cache controller that, responsive to detection of a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, wherein said data transfer is initiated by another of said plurality of caches and not requested by said first cached and includes a second data item that is modified with respect to a corresponding data item in said system memory, stores said second data item in said first cache in association with said address tag and updates said coherency indicator to a second state indicating that said second data item is valid in said first cache and that said first cache, of all of said plurality of caches, is responsible for supplying said second data item in response to a request.

A data processing system, comprising:

• an interconnect;
• a plurality of processors;
• a plurality of caches coupled to said plurality of processor and to said interconnect, wherein a first cache among said plurality of caches includes:
• data storage;
• tag storage that stores an address tag indicating an address of a first data item contained in said data storage;
• a coherency indicator having at least first and second states, wherein said first state indicates that said address tag is valid and that said first data item is invalid;
• and
• a cache controller that, responsive to detection of a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said first state, wherein said data transfer is initiated by another of said plurality of caches and includes a second data item that is modified with respect to a corresponding data item in said system memory, stores said second data item in said first cache in association with said address tag and updates said coherency indicator to a second state indicating that said second data item is valid and that said first cache, of all of said plurality of caches, is responsible for supplying said second data item in response to a request;
• said cache controller comprising means for writing said second data item from said first cache to said system memory responsive to deallocation by said first cache of a cache line containing said second data item.