US 6,275,905 B1 · Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

Abstract

In a multiprocessing computer system, a cache-coherent data transfer scheme that also conserves the system memory bandwidth during a memory read operation is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and sending respective probe responses to the source node. Probe command also causes the node having an updated copy of the cache block to send the cache block to the source node through a read response. The target node, concurrently with the probe command, initiates a read response transmission to send the requested data to the source node. The node having the modified cached copy containing the requested data transmits a memory cancel response to the target node concurrently with the updated copy of the cache block to the source node. The memory cancel response attempts to prevent the target node from sending to the source node the stale data from the system memory. The memory cancel response also causes the target node to send a target done response to the source node. The source node waits for probe responses, read responses and the target done message prior to sending a source done message to the target node.

Claims25

Dependent claims

A multiprocessing computer system comprising:

a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes:
a first processing node configured to generate a read command to read a designated memory location in a memory associated with a second processing node,
wherein said second processing node configured to receive said read command and to responsively transmit a probe command to each of at least one remaining processing node in said plurality of processing nodes regardless of whether a copy of said designated memory location is cached within any of said at least one remaining processing node, and to responsively transmit a first read response to said first processing node including a first data packet containing data from said designated memory location,
wherein said at least one remaining processing node includes a third processing node configured to transmit, in response to said probe command and upon detecting a modified copy of said designated memory location cached within said third processing node, a memory cancel response to said second processing node and a second read response to said first processing node, said second read response including a second data packet containing said modified copy of said designated memory location, and
wherein said memory cancel response causes said second processing node to cancel transmission of said first read response to said first processing node.

2 more elements

In a multiprocessing computer system comprising a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes a first processing node, a second processing node, and at least one remaining processing node including a third processing node, a method for reading data from a memory location in a memory associated with said second processing node, said method comprising:

transmitting a read command from said first processing node to said second processing node to read said data from said memory location;
sending a probe command from said second processing node to each of said at least one remaining processing node in response to receiving said read command by said second processing node regardless of whether a copy of said memory location is cached within any of said at least one remaining processing node, and transmitting a first read response to said first processing node in response to said read command, said first read response including a first data packet containing data from said memory location,
said third processing node transmitting, in response to said probe command and upon detecting a modified copy of said memory location cached within said third processing node, a memory cancel response to said second processing node and a second read response to said first processing node, said second read response including a second data packet containing said modified copy of said memory location, and
said memory cancel response causing said second processing node to cancel transmission of said first read response to said first processing node.

1 more element

Dependencies are inferred from the claim text.

Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

Life of this patent

Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

Life of this patent

Abstract

Claims25