US 6,275,903 B1 · Stack cache miss handling

Abstract

An instruction pipeline is provided which can handle stack cache misses without stalling. The instruction pipeline includes a stack cache fetch stage configured to retrieve data from a stack cache and a data cache fetch stage configured to retrieve data from a data cache. The instruction pipeline writes data out during a write stage that occurs at the end of the instruction pipeline. Thus, instead of stalling on a stack cache miss, the instruction pipeline can continue processing and issuing a data cache request in the data cache fetch stage for the required data. In addition, some embodiments of the invention include a feedback path between the stack cache fetch stage and pipeline stages following the stack cache fetch stage. If the stack cache fetch stage requires data from an address that is also being used by a later pipeline stage, the data in the later pipeline stage is sent to the stack cache fetch stage through the feedback path.

Claims6

Dependent claims

In a stack based computing system utilizing a stack cache and a data cache, a method to handle stack cache misses, said method comprising:

requesting a first data word from said stack cache in a stack cache fetch stage of an instruction pipeline in the stack based computing system;
detecting a stack cache miss;
requesting said first data word from the data cache;
pushing a result computed using said first data word onto the stack;
comparing a memory address of said first data word with a memory address of a second data word in a data cache fetch stage;
retrieving said second data word in place of said first data word if said memory address of said first data word matches said memory address of said second data word;
comparing said memory address of said first data word with a memory address of a third data word in an execution stage of said instruction pipeline;
and
retrieving said third data word in place of said first data word if said memory address of said first data word matches said memory address of said third data word.

6 more elements

Dependencies are inferred from the claim text.

Stack cache miss handling

Life of this patent

Stack cache miss handling

Life of this patent

Abstract

Claims6