Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array
AssigneeIntel Corporation
InventorsEdward Zager, Gregory Mathews
Life of this patent
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Abstract
A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with entries in the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.
Claims4
A computer system comprising a 2n way set associative cache memory subsystem (n>0) including a data array and a corresponding address tag array, characterized by (a) the two arrays being physically disposed in a chip boundary crossing manner, and (b) the two arrays being accessed in a sequential manner, when responding to a read access, and yet the two arrays function as a set associative cache memory,
- the chip boundary crossing manner comprising placing the address tag array inside a microprocessor chip while placing the data array outside the microprocessor chip in a single memory bank,
- the sequential manner comprising accessing the on-chip address tag array first for cache hit/miss determination and for generation of a cache address by combining n address bits with a plurality of set and line denoting address bits in accordance with the results of the cache hit/miss determination, and accessing only one of the 2n ways of the off-chip data array subsequently using the generated cache address.
Dependencies are inferred from the claim text.