Modular and scalable system for signal and multimedia processing

A system which comprises:

• a traffic master;
• an array of memory modules, wherein each memory module is coupled to the traffic master by a data channel, wherein each data channel includes an address path and one or more data paths, wherein the data paths have a common number of data lines;
• and
• an array of processor units each coupled to the traffic master by a data bus to transfer data to and from the memory modules using a shared address space which spans the array of memory modules,
• wherein the traffic master includes:
• a processor interface port for each processor, wherein the processor interface port converts data bus signals into corresponding data channel signals, and also converts data channel signals into corresponding data bus signals;
• a router coupled to the processor interface ports to receive the data channel signals and configured to route the data channel signals to the memory modules, wherein the router is further configured to carry requested data channel signals from the memory modules to the processor interface ports;
• a memory management unit coupled to the processor interface ports to receive address signals, and configured to responsively determine a conflict-free access pattern, wherein the memory management unit is coupled to the router to provide control signals to the router, whereby the router implements the conflict-free access pattern to route data channel signals between the memory modules and the processor interface ports;
• and
• an interrupt control unit coupled to the processor units to provide interrupt signals, wherein the interrupt control unit is configured to assert an interrupt signal if the memory management unit detects a prohibited memory access attempt by a processor unit,
• wherein the array of processor units includes at least one processor unit having a data bus with a number of data lines that exceeds said common number of data lines in the data paths.

A processing system which comprises:

• an array of processor units;
• an array of memory units, wherein each memory unit corresponds to a processor unit;
• a traffic master which couples each memory unit to a processor unit by a corresponding address bus and a corresponding data bus, wherein the corresponding data bus includes one or more data paths having a common bit-width, wherein the traffic master includes:
• one or more data cross-paths which are coupled to corresponding data paths from each of the data busses by a data bridge;
• an address cross-bus which couples to each of the address busses by an address bridge;
• and
• a memory management unit coupled to the address busses to receive address signals and coupled to the data and address bridges to route signals between the processor units and the memory units,
• wherein the array of processor units includes at least one processor unit having a data bus with a bit-width that exceeds said common bit-width of the data paths, and
• wherein said common bit-width is the greatest common divisor (GCD) of the bit-widths of the data busses.