Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising:

• directly coupling the first and second bus devices to the host bus;
• transmitting one or more configuration write commands on the host bus from the processor based on instructions of an operating system, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device;
• capturing the configuration data from the host bus in the first and second bus devices;
• storing the configuration data in one or more configuration registers of the second bus device;
• storing the configuration data in one or more shadow configuration registers of the first bus device;
• transmitting from the processor on the host bus a transaction request directed to an address within the range of addresses assigned to the second bus device;
• and
• determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.

A method of configuring first and second PCI bridges in a computer system having a processor coupled by a host bus to the PCI bridges at substantially the same level of hierarchy, the first PCI bridge coupling a first PCI bus to the host bus and the second PCI bridge coupling a second PCI bus to the host bus, the method comprising:

• transmitting from the processor on the host bus, based on instructions of an operating system, a configuration command that includes a device identifier that identifies the second PCI bridge and a bus identifier that identifies the first PCI bus;
• receiving the configuration command from the host bus at the second PCI bridge;
• and
• responding to the configuration command using the second PCI bridge such that the second PCI bridge appears to the processor to be directly coupled to the first PCI bus at a hierarchy below the first PCI bus when the second PCI bridge is actually indirectly coupled to the first PCI bus via the host bus and the first PCI bridge.

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising:

• directly coupling the first and second bus devices to the host bus;
• transmitting one or more configuration write commands on the host bus from the processor, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device;
• storing the configuration data on the first and second bus devices;
• transmitting from the processor on the host bus a transaction request directed to an address within the range of addresses assigned to the second bus device;
• and
• determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising:

• directly coupling the first and second bus devices to the host bus;
• coupling the first and second bus devices to the host bus without any intervening bus devices;
• transmitting one or more configuration write commands on the host bus from the processor, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device;
• storing the configuration data on the first and second bus devices;
• transmitting from the processor on the host bus a transaction request directed to an address within the range of addresses assigned to the second bus device;
• and
• determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising:

• directly transmitting one or more configuration write commands on the host bus from the processor to the first and second bus devices, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device;
• capturing the configuration data from the host bus in the first and second bus devices;
• storing the configuration data in one or more configuration registers of the second bus device;
• storing the configuration data in one or more shadow configuration registers of the first bus device:
• transmitting from the processor on the host bus a transaction request directed to an address within the range of addresses assigned to the second bus device;
• and
• determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising:

• directly coupling the first and second bus devices to the host bus;
• transmitting one or more configuration write commands on the host bus from the processor to the first and second bus devices without transmitting to any intervening bus devices, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device;
• capturing the configuration data from the host bus in the first and second bus devices;
• storing the configuration data in one or more configuration registers of the second bus device;
• storing the configuration data in one or more shadow configuration registers of the first bus device;
• transmitting from the processor on the host bus a transaction request directed to an address within the range of addresses assigned to the second bus device;
• and
• determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.

A method of configuring first and second PCI bridges in a computer system having a processor coupled by a host bus to the PCI bridges at substantially the same level of hierarchy, the first PCI bridge coupling a first PCI bus to the host bus and the second PCI bridge coupling a second PCI bus to the host bus, the method comprising:

• directly coupling the first and second bus devices to the host bus;
• transmitting from the processor on the host bus a configuration command that includes a device identifier that identifies the second PCI bridge and a bus identifier that identifies the first PCI bus;
• receiving the configuration command from the host bus at the second PCI bridge;
• and
• responding to the configuration command using the second PCI bridge such that the second PCI bridge appears to the processor to be directly coupled to the first PCI bus at a level of hierarchy below the first PCI bus when the second PCI bridge is actually indirectly coupled to the first PCI bus via the host bus and the first PCI bridge.