System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache

A computer, comprising:

• a central processing unit (CPU) coupled to a CPU bus;
• a memory coupled to a memory bus;
• a peripheral device coupled to a peripheral bus;
• and
• a bus interface unit coupled between the CPU bus, the memory bus and the peripheral bus, wherein the bus interface unit is configured to obtain ownership of the CPU bus while forwarding a pre-defined number of snoop cycles upon the CPU bus, and wherein said bus interface unit comprises a controller placed between the peripheral bus and the CPU bus for allowing transmittal of no more than the pre-defined number of snoop cycles before releasing ownership of the CPU bus.

A computer, comprising:

• a central processing unit (CPU) coupled to a CPU bus;
• a memory coupled to a memory bus;
• a peripheral device coupled to a peripheral bus;
• and
• a bus interface unit coupled between the CPU bus, the memory bus and the peripheral bus, wherein the bus interface unit is configured to obtain ownership of the CPU bus while forwarding a pre-defined number of snoop cycles upon the CPU bus, and wherein at least one of the pre-defined number of snoop cycles are presented to a cache storage location within the CPU prior to writing data at the cache storage location to a location within the memory having the same address as the cache storage location.

A method for snooping a cache memory, comprising:

• upon receiving a write cycle by a bus interface unit, forwarding a bus request signal from the bus interface unit to obtain ownership of a central processing unit (CPU) bus by the bus interface unit;
• maintaining the bus request signal and ownership of the CPU bus until after a pre-defined number of snoop cycles are dispatched to the cache memory by the bus interface unit;
• and
• deasserting the bus request signal after the pre-defined number of snoop cycles terminate.

A method for snooping a cache memory, comprising:

• upon receiving a write cycle by a bus interface unit, forwarding a bus request signal from the bus interface unit to obtain ownership of a central processing unit (CPU) bus by the bus interface unit;
• maintaining the bus request signal and ownership of the CPU bus until after a pre-defined number of snoop cycles are dispatched to the cache memory by the bus interface unit;
• and
• configuring a register within the bus interface unit during reset of a computer employing the bus interface unit, wherein the register is configured with a quantity of said pre-defined number of snoop cycles.