Memory access controller

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing a buffer descriptor for each required access transaction for each channel, said descriptor containing a starting address indicator in system memory for the transaction, a length indicator for data involved in the access transaction and a full bit (F-bit) which is set when the corresponding buffer is full;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels, the component not attempting to perform a read access to a buffer for which the F-bit is not set or a write access to a buffer for which the F-bit is set;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing a buffer descriptor for each required access transaction for each channel, said descriptor containing a starting address indicator in system memory for the transaction, a length indicator for data involved in the access transaction and an interrupt (I-bit);
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• a CPU which issues access instructions to the access controller, the controller issuing an interrupt to the CPU after completion of an access transaction for which the corresponding descriptor has the I-bit present;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel, said context memory including a context buffer containing selected information on each required access transaction for each channel and configuration registers for each channel,
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time;
• and
• wherein at least one of said channels is for transferring data in at least one direction between a memory and a peripheral through a serial port, and including a serial module through which the data to be transferred passes, said module performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/peripheral receiving an output from the module.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time;
• and
• wherein at least one of said channels is for transferring data in at least one direction between a memory and a peripheral through a parallel port, and including a parallel module through which the data to be transferred passes, said module performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/peripheral receiving an output from the module.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• a channel arbiter which selects the channel for which said component provides access control at a given time;
• and
• wherein at least one of said channels is for transferring packetized data in at least one direction between a memory and a packetized data source through a packetized data port, and including a packetized data module through which the data to be transferred passes, said module performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/packetized data source receiving an output from the module.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time;
• and
• wherein each channel is for memory accesses in one direction between a memory and a second element, wherein said component includes a first component which controls addressing and data transfer for memory accesses through said channels, and at least one second component through which data passes for at least one channel during a memory access for such channel, the second component performing at least one of (a) buffering data passing through the module, and (b) reformatting the data to be compatible with a format protocol for the memory/second element receiving an output from the second component.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• and
• a channel arbiter which selects the channel for which said component provides access control at a given time;
• and
• wherein at least one of said channels if for transfer of data between a first memory and a second memory of said computer system memory, wherein said context memory includes an indication of a start address in one of said memory from which data to be transferred is read out, an indication of a start address in the other of said memory at which the data is to be written and an indication of the quantity of data to be transferred, wherein said component includes at least one first component for controlling the addressing of said memories and at least one second component for controlling data transfers for said memories, and including a holding register for storing the data to be transferred between a read access to said one memory and a write access to said other memory.

An access controller for a computer system memory, at least portions of which are accessible through a plurality of channels, including:

• a context memory storing information relating to the current state of each channel;
• a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of said component being time shared by said channels;
• a channel arbiter which selects the channel for which said component provides access control at a given time;
• and
• a bus through which transfers for said system memory pass, said component controlling at least selected data transfers through said bus;
• and
• wherein at least selected memory components of said system memory are connected to transfer data with at least one other system component without passing through said bus, said component providing controls for each such transfer.

A method for controlling the transfer of variable length packetized data (VLPD) from a VLPD source to a system memory including:

• providing N channels though which said transfer of VLPD may be effected, where N is an integer greater than one, each of said channels controlling transfers to buffers of different size in said system memory;
• indicating the availability of a buffer for each channel to receive data;
• receiving an indication of the size of each VLPD to be transferred;
• utilizing said availability indicator and size indication to determine the channel for the smallest available buffer in which the VLPD to be transferred will fit;
• and
• utilizing the determined channel to store the VLPD in said smallest available buffer.