Apparatus for performing packed shift operations

A microprocessor comprising:

• a barrel shifter to shift a first packed data having a first plurality of elements represented by a first plurality of bits by less than N digits to produce a second packed data having a second plurality of elements represented by a second plurality of digits;
• a correction circuit to generate a third plurality of digits, each of said third plurality of digits corresponding to one of said second plurality of digits, and to generate a fourth plurality of digits corresponding to said second plurality of elements, each of said fourth plurality of digits indicating whether to replace at least one of said second plurality of digits with at least one of said third plurality of digits;
• and
• a first plurality of muxes, each of said first plurality of muxes having a first input coupled to receive one of said second plurality of digits, a second input coupled to receive one of said third plurality of digits, a select input coupled to receive one of said fourth plurality of digits, and an output, each output corresponding to a digit of a shifted packed result.

A circuit comprising:

• a barrel shifter to shift a first packed data having a first plurality of elements represented by a first plurality of digits to produce a second packed data having a second plurality of elements, represented by a second plurality of digits;
• a correction circuit to generate a third plurality of digits, and to generate a fourth plurality of digits corresponding to said second plurality of elements, said fourth plurality of digits indicating whether to replace at least one of said second plurality of digits with at least one of said third plurality of digits;
• and
• a first plurality of muxes, each of said first plurality of muxes having a first input coupled to receive one of said second plurality of digits, a second input coupled to receive one of said third plurality of digits, a select input coupled to receive one of said fourth plurality of digits, and an output, each output corresponding to a digit of a shifted packed result.

An apparatus comprising:

• a shifter to shift a quantity of elements of a first data having a plurality of elements represented by a first plurality of digits, responsive to a received control instruction, to produce a second data represented by a second plurality of digits, the quantity of elements shifted being determined by the received control instruction;
• a correction circuit to generate a third plurality of digits and to generate a fourth plurality of digits corresponding to the quantity of elements, each of the fourth plurality of digits indicating whether to replace at least one of the second plurality of digits with at least one of the third plurality of digits;
• and
• a first plurality of multiplexers, each of the first plurality of multiplexers having a first input coupled to receive one of the second plurality of digits, a second input coupled to receive one of the third plurality of digits, a select input coupled to receive at least one of the fourth plurality of digits and an output corresponding to a digit of a shifted element from the quantity of elements.