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US 6,275,555 B1Granted
Digital delay locked loop for adaptive de-skew clock generation
AssigneeIntel Corporation
InventorHongjiang Song
Life of this patent
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Abstract
An apparatus including a phase detector to detect a phase difference between an output clock signal and a local reference clock signal comprising a first sampling circuit and a second sampling circuit to cross-sample the output clock signal and the local reference clock signal respectively and a comparator circuit coupled to the two sampling circuits that detects the phase difference.
Claims35
An apparatus comprising:
- a phase detector to detect a phase difference between an output clock signal and a local reference clock signal, having (1) a first sampling circuit and a second sampling circuit to sample the output clock signal by using the reference clock signal, and sample the local reference clock signal by using the output clock signal, respectively and (2) a comparator circuit coupled to the two sampling circuits that detects the phase difference, the first sampling circuit to produce a pulse in response to a transition in the reference clock signal, for sampling the output clock signal;
- and
- a digitally controlled delay line (DCDL) coupled to the output clock signal to adaptively adjust a delay to compensate for the phase difference.
A method of de-skew clock generation comprising:
- detecting a phase difference between output and local reference clocks;
- and
- adjusting a delay to compensate for the phase differences, by controlling a fine digital delay line (FDDL) and a coarse digital delay line (CDDL) to adjust the delay, wherein underflow (U) and overflow (O) flag signals from the FDDL control a multi-bit up/down binary counter which controls the CDDL.
A system comprising:
- a processor;
- and
- a peripheral controller coupled to the processor, the processor adapted to access data from the peripheral controller, the peripheral controller comprising a de-skew clock generation circuit comprising:
- a phase detector to detect a phase difference between output and local reference clocks, the detector having (1) a first sampling circuit and a second sampling circuit to sample the output clock signal by using the reference clock signal, and sample the local reference clock signal by using the output clock signal, respectively, and (2) a comparator circuit coupled to the two sampling circuits that detects the phase difference, the first sampling circuit to produce a pulse in response to a transition in the local reference clock signal, for sampling the output clock signal;
- and
- a digitally controlled delay line (DCDL) to adaptively adjust a delay in the output clock signal to compensate for the phase difference.
3 more elements
An apparatus comprising:
- a phase detector to detect a phase difference between an output clock signal and a local reference clock signal, having (1) a first sampling circuit and a second sampling circuit to sample the output clock signal by using the reference clock signal, and sample the local reference clock signal by using the output clock signal, respectively, and (2) a comparator circuit coupled to the two sampling circuits that detects the phase difference;
- a digitally controlled delay line (DCDL) coupled to the output clock signal to adaptively adjust a delay to compensate for the phase difference,
- wherein the digitally controlled delay line (DCDL) comprises a fine digital delay line (FDDL) and a coarse digital delay line (CDDL) and wherein the CDDL further comprises a plurality of differential multiplexers coupled to coarse delay buffer bits and to a multi-bit up/down binary counter, and configured to select a delay according to a corresponding bit in the up/down binary counter.
Dependencies are inferred from the claim text.