Digital PLL circuit and clock generation method

A digital PLL circuit comprising:

• a PLL circuit comprising a reference oscillator, a voltage-controlled oscillator and a 1/N frequency divider dividing the oscillation output of said voltage-controlled oscillator by means of said 1/N frequency divider, comparing the phases of an output signal of said 1/N frequency divider and an output signal of said reference oscillator, controlling the oscillator frequency of said voltage-controlled oscillator, and extracting an oscillation output of said voltage-controlled oscillator;
• a signal generation circuit generating a plurality of output signals having the same frequency as a frequency from said voltage-controlled oscillator of said PLL circuit but differing phase;
• and
• a phase detection circuit comprising a signal selecting circuit that is capable of selecting a signal from said signal generation circuit a variable frequency divider circuit that divides the frequency of an output of said signal selecting circuit, a phase comparator circuit that compares the phases of a reference signal and the output signal from said variable frequency divider circuit, an up/down counter that detects a difference in phase of said phase comparator circuit, a digital filter that is provided between said up/down counter and said signal selecting circuit, said phase detection circuit selecting the signal from said signal generation circuit based on the output of said up/down counter;
• wherein in said phase detection circuit a clock that is synchronized with the phase of said reference signal is obtained by said phase detection circuit, and said oscillation output is phase-compared N times by said PLL circuit in a time between two of said reference signals of said phase detection circuit wherein said voltage-controlled oscillator of said PLL circuit is formed by a loop connection of an odd number of inverter circuits in cascade, and said PLL circuit being formed such as to satisfy the following relationship between the allowable jitter time of said clock, an oscillation period of said reference oscillator thereof, the divisor of said 1/N frequency divider circuit, and the number of inverter circuit stages of said voltage-controlled oscillator (VCO) thereof, wherein the allowable clock jitter time
• >(Reference oscillator period){(Divisor of 1/N frequency divider)×(Number of inverter circuit stages in VCO)×2}.

A digital PLL circuit comprising:

• a PLL circuit comprising a reference oscillator, a voltage-controlled oscillator and a 1/N frequency divider which divisor is unvaried, said 1/N frequency divider dividing an oscillation output of said voltage-controlled oscillator comparing the phases of an output signal of said 1/N frequency divider, comparing the phases of an output signal of said 1/N frequency divider and an output signal of said reference oscillator, controlling the oscillation frequency of said voltage-controlled oscillator, and extracting an oscillation output of said voltage-controlled oscillator;
• a signal generation circuit generating a plurality of output signals having the same frequency as a frequency from said voltage-controlled oscillator of said PLL circuit but differing phase;
• a phase detection circuit comprising a signal selecting circuit that is capable of selecting a signal from said signal generation circuit, a variable frequency divider circuit that divides the frequency of an output of said signal selecting circuit, said output of said signal selecting circuit being also an output of said digital PLL circuit a phase comparator circuit that compares the phases of a reference signal and the output signal from said variable frequency divider circuit, an up/down counter that detects a difference in phase of said phase comparator circuit, a digital filter that is provided between said up/down counter and said signal selecting circuit, said phase detection circuit selecting the signal from said signal generation circuit based on the output of said up/down counter;
• and
• a frequency detection circuit detecting a frequency of said reference signal of said phase detection circuit, and controlling said variable frequency divider circuit provided in said phase detection circuit based on a detection result obtained by said frequency detection circuit;
• wherein in said phase detection circuit a clock that is synchronized with the phase of said reference signal is obtained by said phase detection circuit, and said oscillation output is phase-compared N times by said PLL circuit in a time between two of said reference signals of said phase detection circuit.

A digital PLL circuit comprising:

• a PLL circuit comprising a reference oscillator, a voltage-controlled oscillator and a 1/N frequency divider which divisor is unvaried, said 1/N frequency divider dividing an oscillation output of said voltage-controlled oscillator comparing the phases of an output signal of said 1/N frequency divider, comparing the phases of an output signal of said 1/N freqcuency divider and an output signal of said reference oscillator, controlling the oscillation frequency of said voltage-controlled oscillator, and extracting an oscillation output of said voltage-controlled oscillator;
• a signal generation circuit generating a plurality of output signals having the same frequency as a frequency from said voltage-controlled oscillator of said PLL circuit but differing phase;
• a phase detection circuit comprising a signal selecting circuit that is capable of selecting a signal from said signal generation circuit, a variable frequency divider circuit that divides the frequency of an output of said signal selecting circuit, a phase comparator circuit that compares the phases of a reference signal and the output signal from said variable frequency divider circuit, an up/down counter that detects a difference in phase of said phase comparator circuit, a digital filer that is provided between said up/down counter and said signal selecting circuit, said phase detection circuit selecting the signal from said signal generation circuit based on the output of said up/down counter;
• and
• a frequency detection circuit detecting a frequency of said reference signal of said phase detection circuit, and controlling said variable frequency divider circuit provided in said phase detection circuit based on a detection result obtained by said frequency detection circuit;
• wherein in said phase detection circuit a clock that is synchronized with the phase of said reference signal is obtained by said phase detection circuit, and said oscillation output is phase-compared N times by said PLL circuit in a time between two of said reference signals of said phase detection circuit, and
• wherein said voltage-controlled oscillator of said PLL circuit is formed by a loop connection of an odd number of inverter circuits in cascade, and said digital PLL circuit being formed so as to satisfy the following relationship between the allowable jitter time of said clock, an oscillation period of said reference oscillator thereof, the divisor of said 1/N frequency divider circuit, and the number of inverter circuit stages of said voltage-controlled oscillator (VCO) thereof, wherein the allowable clock jitter time
• >(Reference oscillator period){(Divisor of 1/N frequency divider)×(Number of inverter circuit stages in VCO)×2}.

A clock generation method of a digital PLL circuit comprising a PLL circuit having a voltage-controlled oscillator and an unvaried frequency divider, a phase detection circuit having a variable frequency divider and detecting a phase of an output signal of said PLL circuit, and a frequency detection circuit detecting a frequency of a reference signal of said phase detection circuit, the method comprising:

• a step of controlling said variable frequency divider provided in said phase detection circuit based on a detection result obtained by said frequency detection circuit;
• a step of dividing an oscillation output of said PLL circuit by said unvaried frequency divider of said PLL circuit, and generating a plurality of output signals having the same frequency as a frequency from said voltage-controlled oscillator of said PLL circuit but differing phase;
• a step of comparing a phase between a reference signal of said phase detection circuit and an output signal from said variable frequency divider of said phase detection circuit and detecting a phase difference between said two signals;
• and
• a step of selecting a signal from said plurality of output signals so as to eliminate said phase difference between said output signal of said variable frequency divider of said phase detection circuit and said reference signal of said phase detection circuit, based on said phase detection result, said signal selected from said plurality of output signals being also an output of said digital PLL circuit.