Methods and apparatus for synchronizing a clock
AssigneeMadge Networks Limited
InventorsDuncan McDougall Greatwood, Philip Geoffrey Claridge
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Abstract
A method and apparatus for synchronizing a clock between first and second logic blocks (20,21) connected via an asynchronous bus (22). The second logic block includes a clock signal generator (9) responsive to an input synchronizing signal to generate a clock signal synchronized with the synchronizing signal. Data is transferred in blocks from the first logic block (20) to the second logic block (21) across the asynchronous bus (22), the receipt of a data block by the second logic block (21) being used to generate the synchronizing signal.
Claims21
A method of synchronizing a clock between first and second logic blocks connected via an asynchronous bus wherein said second logic block includes a clock signal generator responsive to an input synchronizing signal to generate a clock signal synchronized with said synchronizing signal, the method comprising transferring data in blocks from said first logic block to said second logic block across said asynchronous bus;
- and utilizing the receipt of a data block by said second logic block to generate said synchronizing signal in said second logic block, wherein said synchronizing signal is generated at a time of receipt of said data block.
Apparatus for synchronizing a clock between first and second logic blocks connected by an asynchronous bus wherein said second logic block includes a clock signal generator responsive to an input synchronizing signal to generate a clock signal synchronized with said input synchronizing signal, the apparatus comprising a first data transfer controller on said first logic block for controlling transfer of data in blocks across said asynchronous bus;
- and a data block receipt detector on said second logic block for detecting the receipt of a data block and for generating a synchronizing signal related to the receipt of the data block, wherein said synchronizing signal is generated at a time of receipt of said data block and is then fed to said clock signal generator on said second logic block.
Dependencies are inferred from the claim text.