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US 6,275,547 B1Granted
Clock recovery circuit
AssigneeNEC Corporation
InventorTakanori Saeki
Life of this patent
Estimating the term…
Abstract
A clock recovery circuit capable of shortening time needed to obtain a synchronized state includes a first synchronous delay circuit to which a reference clock and data are input and which outputs a first clock, and a second synchronous delay circuit to which the reference clock and a signal obtained by inverting the data by an inverter are input and which outputs a second clock. The first and second clocks are combined by a pulse combining circuit for producing an extracted clock. The extracted clock serves as the latch timing of a latch circuit.
Claims16
A clock recovery circuit comprising:
- (a) a first synchronous delay circuit, to which a reference clock and data are input, for outputting a first clock;
- (b) an inverter for inverting the data and outputting inverted data;
- (c) a second synchronous delay circuit, to which the reference clock and inverted data are input, for outputting a second clock;
- (d) a delay circuit, to which data is input, for outputting delayed data;
- (e) a pulse combining circuit, to which the first clock and the second clock are input, for combining the first and second clocks and outputting the result as an extracted clock;
- and
- (f) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data and outputting the latched data as reproduced data;
- (g) wherein said first synchronous delay circuit comprises:
- (g1) a first delay line, to which the reference clock is input, comprising at least one first individual delay circuit;
- (g2) a first selection circuit array comprising at least one first individual selection circuit, to which the reference clock output by a respective one of the first individual delay circuits is input and which is rendered conductive based upon the data, for generating a first generated reference clock;
- and
- (g3) a first NAND gate, to which the data and the first generated reference clock are input, for outputting the first clock;
- and
- (h) wherein said second synchronous delay circuit comprises:
- (h1) a second delay line, to which the reference clock is input, comprising at least one second individual delay circuit;
- (h2) a second selection circuit array comprising at least one second individual selection circuit, to which the reference clock output by a respective one of the second individual delay circuits is input and which is rendered conductive based upon the inverted data, for generating a second generated reference clock;
- and
- (h3) a second NAND gate, to which the inverted data and the second generated reference clock are input, for outputting the second clock.
15 more elements
A clock recovery circuit comprising:
- (a) a first synchronous delay circuit, to which a reference clock and data are input, for outputting a first clock;
- (b) an inverter for inverting the data and outputting inverted data;
- (c) a second synchronous delay circuit, to which the reference clock and the inverted data are input, for outputting a second clock;
- (d) a delay circuit, to which the data is input, for outputting delayed data;
- (e) a pulse combining circuit, to which the first clock and the second clock are input, for combining the first and second clocks and outputting the result as an extracted clock;
- and
- (f) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data and outputting the latched data as reproduced data;
- (g) wherein said first synchronous delay circuit comprises:
- (g1) a first delay line, to which the reference clock is input, comprising at least one first individual delay circuit;
- (g2) a first selection circuit array comprising at least one first individual selection circuit, to which the reference clock and the reference clock output by a respective one of the first individual delay circuits are input and which is rendered conductive based upon the data, for generating a first generated reference clock;
- (g3) a second delay line, to which the clock output by each first individual selection circuit is input, comprising at least one second individual delay circuit;
- and
- (g4) a first NAND gate, to which the data and the first generated reference clock are input;
- and
- (h) wherein said second synchronous delay circuit comprises:
- (h1) a third delay line, to which the reference clock is input, comprising at least one third individual delay circuit;
- (h2) a second selection circuit array comprising at least one second individual selection circuit, to which the reference clock and the reference clock output by a respective one of the third individual delay circuits are input and which is rendered conductive based upon the inverted data, for generating a second generated reference clock;
- (h3) a fourth delay line, to which the reference clock output by each second individual selection circuit is input, comprising at least one fourth individual delay circuit;
- and
- (h4) a second NAND gate, to which the inverted data and the second generated reference clock are input.
17 more elements
A clock recovery circuit comprising:
- (a) a synchronous delay circuit, to which a reference clock is input;
- (b) a first oscillator, to which data is input, for outputting a first clock;
- (c) an inverter for inverting the data and outputting inverted data;
- (d) a second oscillator, to which the inverted data is input, for outputting a second clock;
- (e) a pulse combining circuit for combining the first clock and the second clock and outputting the result as an extracted clock;
- (f) a delay circuit, to which the data is input, for outputting delayed data;
- and
- (g) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data and outputting the latched data as reproduced data;
- (h) wherein said synchronous delay circuit comprises:
- (h1) a first delay line, to which the reference clock is input, comprising at least one first individual delay circuit;
- and
- (h2) a first selection circuit array comprising at least one first individual selection circuit, to which the reference clock and the reference clock output by a respective one of the first individual delay circuits are input;
- (i) wherein said first oscillator comprises:
- (i1) a second selection circuit array, to which the reference clock output by each first individual selection circuit is input, comprising at least one second individual selection circuit;
- (i2) a second delay line, to which the reference clock output from each second individual selection circuit is input, comprising at least one second individual delay circuit;
- and
- (i3) a first NAND gate, to which the data and the reference clock that is output by the second delay line are input, for outputting the first clock to said pulse combining circuit;
- and
- (j) wherein said second oscillator comprises:
- (j1) a third selection circuit array, to which the reference clock output by each first individual selection circuit is input, comprising at least one third individual selection circuit;
- (j2) a third delay line, to which the reference clock output from each third individual selection circuit is input, comprising at least one third individual delay circuit;
- and
- (j3) a second NAND gate, to which the inverted data and the reference clock that is output by said third delay line are input, for outputting the second clock to said pulse combining circuit.
20 more elements
A clock recovery circuit comprising:
- (a) a synchronous delay circuit, to which data is input;
- (b) a first oscillator, to which the data is input, for outputting a first clock;
- (c) an inverter, to which the data is input, for outputting inverted data;
- (d) a second oscillator, to which the inverted data is input, for outputting a second clock;
- (e) a pulse combining circuit, to which the first clock and the second clock are input, for combining the first and second clocks and outputting the result as an extracted clock;
- (f) a delay circuit, to which the data is input, for outputting delayed data;
- and
- (g) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data and outputting the latched data as reproduced data;
- (h) wherein said synchronous delay circuit comprises:
- (h1) a first delay line, to which the data is input, comprising at least one first individual delay circuit;
- and
- (h2) a first selection circuit array comprising at least one first individual selection circuit, to which the data and the data output by a respective one of the first individual delay circuit are input;
- (i) wherein said first oscillator comprises:
- (i1) a second selection circuit array, to which the data output by each first individual selection circuit is input, comprising at least one second individual selection circuit;
- (i2) a double second delay line, to which the data output from each second individual selection circuit is input, comprising at least one second individual delay circuit;
- and
- (i3) a first NAND gate, to which the inverted data and the data that is output by the double second delay line are input, for outputting the first clock to said pulse combining circuit;
- and
- (j) wherein said second oscillator comprises:
- (j1) a third selection circuit array, to which the data output by each first individual selection circuit is input, comprising at least one third individual selection circuit;
- (j2) a double third delay line, to which the data output from each third individual selection circuit is input, comprising at least one third individual delay circuit;
- and
- (j3) a second NAND gate, to which the data and the data that is output by the double third delay line are input, for outputting the second clock to said pulse combining circuit.
20 more elements
A clock recovery circuit comprising:
- (a) a first synchronous delay circuit, to which a data signal is input, for outputting a first clock;
- (b) an inverter for inverting the data signal and outputting an inverted data signal;
- (c) a second synchronous delay circuit, to which the inverted data signal is input, for outputting a second clock;
- (d) a delay circuit, to which the data signal is input, for outputting a delayed data signal;
- (e) a pulse combining circuit, to which the first clock and the second clock are input, for combining the first and second clocks and outputting the result as an extracted clock;
- and
- (f) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data signal and outputting the latched data signal as a reproduced data signal;
- (g) wherein said first and second synchronous delay circuits are mutually complementary synchronous multi-step delay circuits outputting first and second output signals synchronized with the data signal during a period of time which corresponds to a first state and a second state of the data signal, respectively, as a pulse signal having a pulse period substantially shorter than the minimal period of the first and second states of the data signal so as to minimize the time period needed to reach synchronization.
5 more elements
A clock recovery circuit comprising:
- (a) a synchronous multi-step delay circuit, to which a reference clock is input;
- (b) a first oscillator, to which a data signal is input, for outputting a first clock;
- (c) an inverter for inverting the data signal and outputting an inverted data signal;
- (d) a second oscillator, to which the inverted data signal is input, for outputting a second clock;
- (e) a pulse combining circuit for combining the first clock and the second clock and outputting the result as an extracted clock;
- (f) a delay circuit, to which the data signal is input, for outputting a delayed data signal;
- and
- (g) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data signal and outputting the latched data signal as a reproduced data signal;
- (h) wherein said synchronous multi-step delay circuit comprises an array of individual delay circuits, each of which provides a generated reference clock to be supplied to each of the first and second oscillators,
- (i) wherein said first and second oscillators are mutually complementary synchronous oscillators outputting first and second output signals synchronized with the data signal during a period of time which corresponds to a first state and a second state of the data signal, respectively, as a pulse signal having a pulse period substantially shorter than the minimal period of the first and second states of the data signal so as to minimize the time period needed to reach synchronization.
7 more elements
A clock recovery circuit comprising:
- (a) a synchronous multi-step delay circuit, to which a data signal is input;
- (b) a first oscillator, to which the data signal is input, for outputting a first clock;
- (c) an inverter, to which the data signal is input, for outputting an inverted data signal;
- (d) a second oscillator, to which the inverted data signal is input, for outputting a second clock;
- (e) a pulse combining circuit, to which the first clock and the second clock are input, for combining the first and second clocks and outputting the result as an extracted clock;
- (f) a delay circuit, to which the data signal is input, for outputting a delayed data signal;
- and
- (g) a data-type flip-flop, having a clock terminal to which the extracted clock is input, for latching the delayed data signal and outputting the latched data as reproduced data signal;
- (h) wherein said synchronous multi-step delay circuit comprises an array of individual delay circuits, each of which provides a generated reference clock to be supplied to each of the first and second oscillators,
- (i) wherein said first and second oscillators are mutually complementary synchronous oscillators outputting first and second output signals synchronized with the data signal during a period of time which corresponds to a first state and a second state of the data signal, respectively, as a pulse signal having a pulse period substantially shorter than the minimal period of the first and second states of the data signal so as to minimize the time period needed to reach synchronization.
7 more elements
Dependencies are inferred from the claim text.