US 6,275,508 B1 · Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (SAPNA)

Abstract

A technique and system for manipulating, converting or adapting datagram headers as required during traverse from one interface of a networking device to another, by novel clocked micro-sequencing and selection amongst input and output FIFO data streams, through dividing input serial data streams into small groups of FIFO input data streams and feeding the groups parallely into a matrix of a multilane highway of header unit input data, constant data pattern and computational unit busses controlled by such micro-sequencing so as to enable such processing of packet datagram headers and the like at very high wire speed, but using low clock speeds, and in a scalable manner.

Claims32

Dependent claims

A method of changing and manipulating datagram headers of packets of serial data streams of predetermined rate as required during traverse from one interface of a networking device to another, that comprises, dividing input FIFO serial data streams into a plurality of smaller successive groups of bytes of data;

forming a matrix of successive multi-lane highway busses for each of input data, data patterns, computational units, and constant bus lines;
applying each of the successive groups of bytes of input data to a corresponding successive input data highway bus lane and in a parallel fashion;
connecting computational bus lines of the matrix to output FIFOs corresponding respectively to the input FIFOs and through respective selectors;
clock-sequencing the operation of the selectors in accordance with various predetermined logic sequences for switching in the matrix the selection of data fed through the selectors to their output FIFOs in desired combinations selected from the FIFO input data, the results of the computational units, and the data patterns, and thereby manipulating the datagram header data stream as desired;
and setting the clocking rate to a value low compared to the data stream rate.

2 more elements

Apparatus for changing and manipulating datagram headers of packets of serial data streams as required during traverse from one interface of a networking device to another, having, in combination, a plurality of input serial data stream FIFOs divided into a plurality of smaller successive groups of bytes of data;

a matrix of successive multi-lane highway busses for each of input data, data patterns, computational units, and constant bus lines;
means for applying each of the successive groups of bytes of input data to a corresponding successive input data highway bus lane and in a parallel fashion;
means for connecting computational bus lines of the matrix to a plurality of output FIFOs corresponding respectively to the input FIFOs and through respective selectors;
a clock-controlled sequencer for switching the selectors in accordance with various predetermined logic sequences to select data fed through the selectors to their output FIFOs in desired combinations selected from the FIFO input data, the results of the computational units, and the data patterns, and thereby to manipulate the original datagram header data stream as desired;
and means for setting the clocking rate to a value low compared to the data stream rate.

2 more elements

Dependencies are inferred from the claim text.

Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (SAPNA)

Life of this patent

Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (SAPNA)

Life of this patent

Abstract

Claims32