US 6,275,491 B1 · Programmable architecture fast packet switch

Abstract

A programmable fast packet switch testbed (10) for use in the evaluation of prototype architectures and traffic management algorithms is disclosed. The programmable switch (10) is arranged as an add-on peripheral to a conventional computer system including a host central processing unit (CPU) (2). The switch (10) includes a plurality of port processors (14) in communication with port interfaces (12); each of the port interfaces (12) is a conventional interface for high data rate communication, while the port processors (14) are programmable logic devices. The switch fabric is realized in a multiple slice fashion, by multiple programmable logic devices (18). A central arbiter (30), also realized in programmable logic, controls routing of cells within the switch (10). Programming of the port processors (14), fabric slices (18), and arbiter (30) is effected by downloading, into these devices, bit-streams supplied by the host CPU (2) that define the switch architecture, including selection of input or output queuing and the fabric type, along with the implementation of traffic management algorithms in the port processors (14), fabric slices (18), and arbiter (30). Each of the port processors (14), fabric slices (18), and arbiter (30) also contain memory locations for storing results of operation, which are read by the management port (24) over a management bus (COMET), and may then be forwarded to the host CPU (2), without interfering with switch traffic. The programmable switch (10) is therefore capable of full speed operation as a fast packet switch, thus providing accurate evaluation results.

Claims21

Dependent claims

A programmable fast packet switch, comprising:

a plurality of port interfaces, for receiving message cells from and transmitting message cells to external network nodes;
a plurality of port processors, each coupled to one of the plurality of port interfaces and comprised of programmable logic, for generating routing labels for message cells received at its associated port interface, and for applying outgoing message cells to its associated port interface;
a switch fabric, coupled to each of the plurality of port processors, and comprised of programmable logic, for receiving message cells from the plurality of port processors and for routing the message cells to the plurality of port processors;
an arbiter, comprised of programmable logic, for controlling the communication of message cells among the plurality of port processors and the switch fabric responsive to the routing labels generated by the plurality of port processors;
and
a management port, for receiving programming data from a host computer and for programming the plurality of port processors, the switch fabric, and the arbiter responsive to the received programming data.

3 more elements

A method of evaluating the operation of a programmable fast packet switch according to a selected architecture, wherein the programmable fast packet switch is comprised of a plurality of port interfaces for receiving and transmitting message cells, a plurality of port processors associated with the port interfaces and coupled to a switch fabric, and an arbiter coupled to the port processors and to the switch fabric for controlling the routing of message cells therethrough, the method comprising the steps of:

programming logic in the switch fabric, in the arbiter, and in the plurality of port processors, to operate according to the selected architecture;
applying message traffic to at least one of the plurality of port interfaces, the message traffic including message packets addressed to others of the plurality of port interfaces;
operating the programmable fast packet switch to route the applied message traffic among the plurality of port interfaces;
during the operating step, storing result information in each of the switch fabric, arbiter, and plurality of port processors;
and
retrieving the stored result information from the switch fabric, arbiter, and plurality of port processors.

3 more elements

A computer system, comprising:

a host central processing unit;
a system bus;
and
a programmable fast packet switch, coupled to the system bus, and comprising:
a bus interface, coupled to the system bus;
a plurality of port interfaces, for receiving message cells from and transmitting message cells to external network nodes;
a plurality of port processors, each coupled to one of the plurality of port interfaces and comprised of programmable logic, for generating routing labels for message cells received at its associated port interface, and for applying outgoing message cells to its associated port interface;
a switch fabric, coupled to each of the plurality of port processors, and comprised of programmable logic, for receiving message cells from the plurality of port processors and for routing the message cells to the plurality of port processors;
an arbiter, comprised of programmable logic, for controlling the communication of message cells among the plurality of port processors and the switch fabric responsive to the routing labels generated by the plurality of port processors;
and
a management port, for receiving programming data from a host computer and for programming the plurality of port processors, the switch fabric, and the arbiter responsive to the received programming data.

8 more elements

Dependencies are inferred from the claim text.

Programmable architecture fast packet switch

Life of this patent

Programmable architecture fast packet switch

Life of this patent

Abstract

Claims21