US 6,275,446 B1 · Clock generation circuits and methods

Abstract

Clock generator circuits containing a delay circuit having at least one delay element and at least one bypass are arranged to activate the bypass in response to a first logic level presented at the input of the delay circuit and to deactivate the bypass in response to a second logic level presented at the input of the delay circuit. Such clock generators are useful in synchronous memory devices for generating internal clock signals of fixed pulse width from an external clock signal. The internal clock signal is generated from a triggering event, such as a rising edge of the external clock signal, and has a pulse width determined by the delay time of the delay element. The first logic level is generated in response to the beginning of an output pulse of the clock generator while the second logic level is generated in response to the completion of an output pulse of the clock generator. Bypassing the delay element upon completion of an output pulse more quickly prepares the clock generator to receive the next triggering event.

Claims53

Dependent claims

A clock generator, comprising:

an input buffer for receiving an external clock signal;
and
a one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal, wherein the one-shot circuit comprises a delay circuit having at least one delay element and at least one associated bypass;
wherein the one-shot circuit generates a first logic level in response to a completion of an output pulse and presents the first logic level to an input of the delay circuit, further wherein the first logic level activates the at least one associated bypass and is passed to an output of the delay circuit substantially without delay;
and
wherein the one-shot circuit generates a second logic level in response to a beginning of an output pulse and presents the second logic level to the input of the delay circuit, further wherein the second logic level deactivates the at least one associated bypass and is passed to the output of the delay circuit at a time delta substantially equal to a predetermined delay time of the at least one delay element.

3 more elements

A clock generator, comprising:

an input buffer for receiving an external clock signal;
and
a one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal, wherein the one-shot circuit comprises:
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer;
and
a delay circuit having an input and an output, at least one delay element having a predetermined delay time coupled in series between the input and the output of the delay circuit, and at least one bypass coupled between the input and the output of the delay circuit in parallel with the at least one delay element, wherein the output of the delay circuit is coupled to the reset input of the SR latch, further wherein the input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse and to receive a second logic level indicative of a beginning of an output pulse;
wherein the first logic level activates the at least one bypass and is passed from the input of the delay circuit to the output of the delay circuit substantially without delay;
and
wherein the second logic level deactivates the at least one bypass is passed from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to the predetermined delay time of the at least one delay element.

6 more elements

A clock generator, comprising:

an input buffer;
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer;
a delay circuit having an input and an output, wherein the output of the delay circuit is coupled to the reset input of the SR latch;
and
an inverter coupled between the output of the NAND SR latch and the input of the delay circuit;
wherein the delay circuit comprises:
at least one non-inverting delay element coupled between the input and the output of the delay circuit, each having an input and an output;
and
at least one bypass, each having an input, an output and a first pass gate coupled between its input and output, wherein the input of each bypass is coupled to the input of an associated delay element and the output of each bypass is coupled to the output of its associated delay element.

6 more elements

A memory device, comprising:

an array of memory cells;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells;
an address decoder circuit coupled to the row access circuit and the column access circuit;
and
a clock generator for generating an internal clock signal for synchronizing access commands to the array of memory cells, wherein the clock generator comprises:
an input buffer for receiving an external clock signal;
and
a one-shot circuit coupled to the input buffer for providing the internal clock signal in response to the external clock signal, wherein the one-shot circuit comprises:
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer and wherein an output pulse is provided on the output of the SR latch;
and
a delay circuit having an input and an output, wherein the output of the delay circuit is coupled to the reset input of the SR latch, further wherein the input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse of the internal clock signal and to receive a second logic level indicative of a beginning of an output pulse of the internal clock signal, still further wherein the delay circuit comprises:
at least two delay elements coupled in series and having a predetermined delay time, wherein the at least two delay elements are coupled between the input and the output of the delay circuit;
and
at least two bypasses, wherein each bypass is associated with one delay element in a one-to-one relationship, and wherein each bypass is activated in response to the first logic level, thereby passing the first logic level across each delay element substantially without delay, and deactivated in response to the second logic level, thereby passing the second logic level from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to or greater than the predetermined delay time of the at least two delay elements.

12 more elements

A memory device, comprising:

an array of memory cells;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells;
an address decoder circuit coupled to the row access circuit and the column access circuit;
and
a clock generator for generating an internal clock signal for synchronizing access commands to the array of memory cells, wherein the clock generator comprises:
an input buffer for receiving an external clock signal;
a NAND SR latch having a set input, a reset input and an output for providing the internal clock signal, wherein the set input is coupled to an output of the input buffer;
a delay circuit having an input and an output, wherein the output of the delay circuit is coupled to the reset input of the SR latch;
and
an inverter coupled between the output of the NAND SR latch and the input of the delay circuit;
wherein the delay circuit comprises:
at least one non-inverting delay element coupled between the input and the output of the delay circuit, each having an input and an output;
at least one bypass, each having an input, an output and a first pass gate coupled between its input and output, wherein the input of each bypass is coupled to the input of an associated delay element and the output of each bypass is coupled to the output of its associated delay element, further wherein each first pass gate has a first transistor of a first polarity having a gate coupled to a node interposed between the input of the delay circuit an input of a first delay element, and a second transistor of an opposite polarity having a gate coupled to the node through an interposing inverter;
and
at least one second pass gate, wherein a second pass gate is coupled between the output of each delay element and the output of that delay element's associated bypass, further wherein each second pass gate has a first transistor of the first polarity having a gate coupled to the gate of the second transistor of the first pass gate of the associated bypass, and wherein each second pass gate has a second transistor of the opposite polarity having a gate coupled to the gate of the first transistor of the first pass gate of the associated bypass.

13 more elements

A synchronous flash memory device, comprising:

a plurality of memory banks containing non-volatile flash memory cells;
and
a command execution logic coupled to the plurality of memory banks for receiving at least a system clock input signal and for generating commands to control operations performed on the plurality of memory banks, wherein the commands are synchronized to an internal clock signal generated from the system clock input signal by a clock generator;
wherein the clock generator comprises:
an input buffer for receiving the system clock input signal as an external clock signal;
and
a one-shot circuit coupled to the input buffer for providing the internal clock signal in response to the external clock signal, wherein the one-shot circuit comprises:
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer;
and
a delay circuit having an input and an output, at least one delay element having a predetermined delay time coupled in series between the input and the output of the delay circuit, and at least one bypass coupled between the input and the output of the delay circuit in parallel with the at least one delay element, wherein the output of the delay circuit is coupled to the reset input of the SR latch, further wherein the input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse of the internal clock signal and to receive a second logic level indicative of a beginning of an output pulse of the internal clock signal;
wherein the first logic level activates the at least one bypass and is passed from the input of the delay circuit to the output of the delay circuit substantially without delay;
and
wherein the second logic level deactivates the at least one bypass is passed from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to the predetermined delay time of the at least one delay element.

10 more elements

A synchronous flash memory device, comprising:

a plurality of memory banks containing non-volatile flash memory cells;
and
a command execution logic coupled to the plurality of memory banks for receiving at least a system clock input signal and for generating commands to control operations performed on the plurality of memory banks, wherein the commands are synchronized to an internal clock signal generated from the system clock input signal by a clock generator,
wherein the clock generator comprises:
an input buffer for receiving the system clock input signal as an external clock signal;
and
a one-shot circuit coupled to the input buffer for providing the internal clock signal in response to the external clock signal, wherein the one-shot circuit comprises:
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer and wherein an output pulse is provided on the output of the SR latch;
and
a delay circuit having an input and an output, wherein the output of the delay circuit is coupled to the reset input of the SR latch, further wherein the input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse of the internal clock signal and to receive a second logic level indicative of a beginning of an output pulse of the internal clock signal, still further wherein the delay circuit comprises:
at least two delay elements coupled in series and having a predetermined delay time, wherein the at least two delay elements are coupled between the input and the output of the delay circuit;
and
at least two bypasses, wherein each bypass is associated with one delay element in a one-to-one relationship, and wherein each bypass is activated in response to the first logic level, thereby passing the first logic level across each delay element substantially without delay, and deactivated in response to the second logic level, thereby passing the second logic level from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to or greater than the predetermined delay time of the at least two delay elements.

10 more elements

A synchronous flash memory device. comprising:

a plurality of memory banks containing non-volatile flash memory cells;
and
a command execution logic coupled to the plurality of memory banks for receiving at least a system clock input signal and for generating commands to control operations performed on the plurality of memory banks, wherein the commands are synchronized to an internal clock signal generated from the system clock input signal by a clock generator;
wherein the clock generator comprises:
an input buffer for receiving the system clock input signal as an external clock signal;
a NAND SR latch having a set input, a reset input and an output for providing the internal clock signal, wherein the set input is coupled to an output of the input buffer;
a delay circuit having an input and an output, wherein the output of the delay circuit is coupled to the reset input of the SR latch;
and
an inverter coupled between the output of the NAND SR latch and the input of the delay circuit;
wherein the delay circuit comprises:
at least one non-inverting delay element coupled between the input and the output of the delay circuit, each having an input and an output;
at least one bypass, each having an input an output and a first pass gate coupled between its input and output, wherein the input of each bypass is coupled to the input of an associated delay element and the output of each bypass is coupled to the output of its associated delay element, further wherein each first pass gate has a first transistor of a first polarity having a gate coupled to a node interposed between the input of the delay circuit and an input of a first delay element, and a second transistor of an opposite polarity having a gate coupled to the input of the delay circuit through an interposing inverter;
and
at least one second pass gate, wherein a second pass gate is coupled between the output of each delay element and the output of that delay element's associated bypass, further wherein each second pass gate has a first transistor of the first polarity having a gate coupled to the gate of the second transistor of the first pass gate of the associated bypass, and wherein each second pass gate has a second transistor of the opposite polarity having a gate coupled to the gate of the first transistor of the first pass gate of the associated bypass.

11 more elements

A clock generator, comprising:

an input buffer for receiving an external clock signal;
and
a one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal, wherein the one-shot circuit comprises:
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer;
and
a delay circuit having an input and an output, at least one delay element having a predetermined delay time coupled in series between the input and the output of the delay circuit, and at least one bypass coupled between the input and the output of the delay circuit in parallel with the at least one delay element, wherein the output of the delay circuit is coupled to the reset input of the SR latch, further wherein the input of the delay circuit is coupled to receive a first logic level indicative of a completion of an output pulse and to receive a second logic level indicative of a beginning of an output pulse;
wherein each at least one delay element comprises a first inverter, a second inverter, and at least one capacitor interposed between the first inverter and the second inverter;
wherein each at least one associated bypass comprises an input, an output, and a first pass gate coupled between the input and output, further wherein the first pass gate has a first transistor of a first polarity having a gate coupled to a node interposed between the input of the delay circuit and the input of a first delay element, and a second transistor of an opposite polarity having a gate coupled to the node through an interposing inverter;
wherein the input of each bypass is coupled to an input of its associated delay element and the output of each bypass is coupled to an output of its associated delay element;
wherein the first logic level activates the at least one bypass and is passed from the input of the delay circuit to the output of the delay circuit substantially without delay;
and
wherein the second logic level deactivates the at least one bypass is passed from the input of the delay circuit to the output of the delay circuit at a time delta substantially equal to the predetermined delay time of the at least one delay element.

9 more elements

A clock generator, comprising:

an input buffer;
a NAND SR latch having a set input, a reset input and an output, wherein the set input is coupled to an output of the input buffer;
a delay circuit having an input and an output, wherein the output of the delay circuit is coupled to the reset input of the SR latch;
and
an inverter coupled between the output of the NAND SR latch and the input of the delay circuit;
wherein the delay circuit comprises:
at least one non-inverting delay element coupled between the input and the output of the delay circuit, each having an input and an output;
at least one bypass, each having an input, an output and a first pass gate coupled between its input and output, wherein the input of each bypass is coupled to the input of an associated delay element and the output of each bypass is coupled to the output of its associated delay element, further wherein each first pass gate has a first transistor of a first polarity having a gate coupled to a node interposed between the input of the delay circuit and the input of a first delay element, and a second transistor of an opposite polarity having a gate coupled to the node through an interposing inverter;
and
at least one second pass gate, wherein a second pass gate is coupled between the output of each delay element and the output of that delay element's associated bypass, further wherein each second pass gate has a first transistor of the first polarity having a gate coupled to the gate of the second transistor of the first pass gate of the associated bypass, and wherein each second pass gate has a second transistor of the opposite polarity having a gate coupled to the gate of the first transistor of the first pass gate of the associated bypass.

7 more elements

A delay circuit, comprising:

an input;
an output;
at least one delay element having an input and an output, wherein each delay element is coupled between the input and the output of the delay circuit in series with other delay elements;
and
at least one bypass associated with each delay element, each bypass having an input, an output, and a first pass gate coupled between the input and the output of each bypass, wherein the input of each bypass is coupled to the input of its associated delay element and the output of each bypass is coupled to the output of its associated delay element;
wherein each first pass gate is activated in response to a first logic level presented at the input of the delay circuit and each first pass gate is deactivated in response to a second logic level presented at the input of the delay circuit.

3 more elements

A delay circuit, comprising:

an input;
an output;
at least one delay element having an input and an output, wherein each delay element is coupled between the input and the output of the delay circuit in series with other delay elements;
a first pass gate associated with each delay element, wherein each first pass gate has an input and an output, further wherein the input of each first pass gate is coupled to the input of its associated delay element and the output of each first pass gate is coupled to the output of its associated delay element;
a second pass gate associated with each delay element, wherein each second pass gate has an input and an output, further wherein the input of each second pass gate is coupled to the output of its associated delay element and the output of each second pass gate is coupled to the output of the first pass gate associated with the second pass gate's associated delay element;
wherein each first pass gate is activated in response to a first logic level presented at the input of the delay circuit and each first pass gate is deactivated in response to a second logic level presented at the input of the delay circuit;
and
wherein each second pass gate is deactivated in response to the first logic level presented at the input of the delay circuit and each second pass gate is activated in response to the second logic level presented at the input of the delay circuit.

5 more elements

Dependencies are inferred from the claim text.

Clock generation circuits and methods

Life of this patent

Clock generation circuits and methods

Life of this patent

Abstract

Claims53