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US 6,275,445 B1Granted
Synchronous integrated memory
AssigneeInfineon Technologies AG
InventorsStefan Dietrich, Peter Schrögmeier, Torsten Partsch, Christian Weis
Life of this patent
Estimating the term…
Abstract
A memory has data lines through which data connections are connected to groups of memory cells via a synchronizing unit. The synchronizing unit is disposed adjacent to the cell group and has a clock input to which an internal clock signal is fed. In the event of a write access to the memory, the synchronizing unit synchronizes with the internal clock signal data signals that are fed via the data connections and are synchronous with an external clock signal.
Claims4
A synchronous integrated memory, comprising:
- a group of memory cells disposed adjacent to one another;
- at least two data connections for feeding in data signals synchronized with an external clock signal;
- a clock generator having a clock output and generating an internal clock signal available at said clock output;
- data lines connected to said data connections;
- and
- a synchronizing unit disposed adjacent to said group of memory cells, said synchronizing unit connected to said group of memory cells and to said data lines and through which said group of memory cells being connected to said data connections, said synchronizing unit having a clock input connected to said clock output of said clock generator, and, in an event of a write access, synchronizes the data signals that have been fed through said data connections and said data lines with the internal clock signal and feeds the data signals to said group of memory cells.
3 more elements
Dependencies are inferred from the claim text.