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US 6,275,443 B1Granted
Latched row or column select enable driver
AssigneeMicron Technology, Inc.
InventorsCharles L. Ingalls, Huy T. Vo
Life of this patent
Estimating the term…
Abstract
A column latch device uses first and second latches, the first controlling input to the second, to enable a column line in a redundant column line control system for a memory device. A column select signal is selectively passed to the second latch when the first latch receives a predetermined signal from an address comparator which checks an incoming column address against stored defective addresses.
Claims30
A latch device for a memory array, said device comprising:
- an address comparator;
- a first latch having an input and an output, the input of said first latch being controlled by a compare signal from said address comparator;
- a first transistor having a first terminal, a second terminal, and a gate terminal, said gate terminal being coupled to said output of said first latch;
- and
- a second latch having an input and an output, said input of said second latch being coupled to said second terminal of said first transistor, said output of said first latch controlling said first transistor to selectively pass a select signal applied to said first terminal of said first transistor to said second latch, said second latch providing a an enable signal to one of a row and column of a memory array.
2 more elements
A latch device for a memory array, said device comprising:
- a first latch having an input and an output, an input of said first latch being controlled by a compare signal from an address comparator;
- a second latch having an input and an output, said output of said second latch selectively providing an enable signal to one of a row and column of a memory array;
- and
- a first switching device coupled to said output of said first latch and said input of said second latch;
- said switching device receiving a select signal and selectively applying said select signal to said second latch in response to the output of said first latch.
2 more elements
A latch device for a memory array, said device comprising:
- a first latch having an input and an output;
- a first transistor having a first terminal, a second terminal, and a gate terminal, said gate terminal being coupled to said output of said first latch;
- a second latch having an input and an output, said input of said second latch being coupled to said second terminal of said first transistor, an output of said first latch controlling said first transistor to selectively pass a select signal applied to said first terminal of said first transistor to said second latch, said second latch providing an enable signal to a one of a row and column of a memory array;
- a second transistor having a first terminal coupled to said input of said first latch and a second terminal coupled to a first terminal of a third transistor, said second transistor having a gate for receiving a compare signal from an address comparator;
- said third transistor selectively passing a first predetermined voltage potential to said second terminal of said second transistor;
- and
- a fourth transistor having a first terminal coupled to said input of said second latch and a second terminal coupled to a second predetermined voltage potential, said fourth transistor selectively passing said second predetermined voltage to said input of said second latch in response to the output of said first latch.
4 more elements
A processor system comprising:
- a processor;
- and
- a memory device coupled to said processor, said memory device comprising:
- a first latch having an input and an output, an input of said first latch being controlled by a compare signal from an address comparator;
- a second latch having an input and an output, said output of said second latch selectively providing an enable signal to one of a row and column of a memory array;
- and
- a first switching device coupled to said output of said first latch and said input of said second latch;
- said switching device receiving a select signal and selectively applying said select signal to said second latch in response to the output of said first latch.
5 more elements
An integrated memory circuit comprising:
- a die containing a processor and memory device, said memory device containing at least one latch device for controlling an element of a memory array, said at least one latch device comprising:
- a first latch having an input and an output, an input of said first latch being controlled by a compare signal from an address comparator;
- a second latch having an input and an output, said output of said second latch selectively providing an enable signal to an element of a memory array;
- and
- a first switching device coupled to said output of said first latch and said input of said second latch;
- said switching device receiving a select signal and selectively applying said select signal to said second latch in response to the output of said first latch.
3 more elements
A method of operating a memory device, said method comprising;
- receiving a select signal from an address decoder;
- receiving a compare signal from an address comparison circuit;
- controlling the state of a first latch with said compare signal;
- using an output of said first latch to selectively control the passage of said select signal to an input of a second latch and controlling the state of said second latch with said select signal passed to the input of said second latch;
- enabling one of a row and column of a memory array with an output of said second latch.
2 more elements
Dependencies are inferred from the claim text.