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US 6,275,441 B1Granted
Data input/output system for multiple data rate memory devices
AssigneeG-Link Technology
InventorJong-Hoon Oh
Life of this patent
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Abstract
Methods and circuitry for implementing memory devices with I/O architectures that transmit multiple data bits on a data I/O interconnect line during a single clock cycle. Instead of increasing the physical number of I/O interconnect lines to match the increased number of data bits being processed by the multiple data rate memory circuit, a time sharing scheme is devised that processes the multiple bits of data with a minimum number of I/O lines.
Claims12
A memory circuit that operates according to a periodic clock signal, the memory circuit comprising:
- N data registers respectively coupled to N data buses, where N is a positive integer;
- an array of memory cells coupled to the N data buses;
- and
- precharge circuitry coupled to the N data buses, wherein the precharge circuitry is configured not to precharge a data bus during the single period of the periodic clock when two successive bits of the M data bits have the same value;
- wherein the circuit is configured such that each of the N data buses is capable of carrying M bits of data during a single period of the periodic clock signal, where M is a positive integer greater than one;
- wherein each data bus comprises first and second complementary interconnect lines, and wherein, for each of the first and second complementary interconnect lines, the precharge circuitry comprises
- a precharge transistor coupled to an associated interconnect line and configured to pull the associated interconnect line to a precharge potential in response to a precharge control signal;
- and
- precharge logic coupled to compare the value of a current data bit on the associated interconnect line with a value of a succeeding data bit, and to generate the precharge control signal.
6 more elements
A method of transmitting data in a memory circuit that operates according to a periodic clock signal, the memory circuit having
- N data registers respectively coupled to N data buses, where N is a positive integer,
- an array of memory cells coupled to the N data buses, and
- precharge circuitry coupled to the N data buses, wherein the precharge circuitry is configured not to precharge a data bus during the single period of the periodic clock when two successive bits of the M data bits have the same value,
- wherein the circuit is configured such that each of the N data buses is capable of carrying M bits of data during a single period of the periodic clock signal, where M is a positive integer greater than one,
- wherein each data bus comprises first and second complementary interconnect lines, and wherein, for each of the first and second complementary interconnect lines, the precharge circuitry comprises
- a precharge transistor coupled to an associated interconnect line and configured to pull the associated interconnect line to a precharge potential in response to a precharge control signal, and
- precharge logic coupled to compare the value of a current data bit on the associated interconnect line with a value of a succeeding data bit, and to generate the precharge control signal;
- the method of transmitting data comprising:
- transmitting a first bit of data on the interconnect lines during a first portion of a single period of the clock signal;
- and
- transmitting a second bit of data on the interconnect lines during a second portion of the single period of the clock signal.
8 more elements
A method of operating a semiconductor memory device, the semiconductor memory device having
- N data registers respectively coupled to N data buses, where N is a positive integer,
- an array of memory cells coupled to the N data buses, and
- precharge circuitry coupled to the N data buses, wherein the precharge circuitry is configured not to precharge a data bus during the single period of the periodic clock when two successive bits of the M data bits have the same value,
- wherein the circuit is configured such that each of the N data buses is capable of carrying M bits of data during a single period of the periodic clock signal, where M is a positive integer greater than one,
- wherein each data bus comprises first and second complementary interconnect lines, and wherein, for each of the first and second complementary interconnect lines, the precharge circuitry comprises
- a precharge transistor coupled to an associated interconnect line and configured to pull the associated interconnect line to a precharge potential in response to a precharge control signal, and
- precharge logic coupled to compare the value of a current data bit on the associated interconnect line with a value of a succeeding data bit, and to generate the precharge control signal;
- the method comprising:
- selecting a plurality of data in one clock cycle from an array of memory cells in read mode;
- determining a sequence of the plurality of data;
- time shifting each of the plurality of data according to the sequence;
- and
- driving the plurality of data onto a single data bus in the sequence within one clock cycle.
10 more elements
Dependencies are inferred from the claim text.