US 6,275,437 B1Granted

Refresh-type memory with zero write recovery time and no maximum cycle time

AssigneeSamsung Electronics Co., Ltd.

InventorsChang-Rae Kim, Jong-Yul Park, Min-Chul Chung, Sang-Jib Han

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Abstract

A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete. At a convenient time after the end of the external write command (e.g., during the next external write command), a short pulsed write operation transfers the data to the memory cell array.

Claims28

Dependent claims

A semiconductor memory device having a refresh-type memory cell array, the device comprising:

an address buffer to receive external address information and generate an internal address signal during a read/write operation;
a write address register to store the internal address signal received by the address buffer during an external write operation, and output that stored internal address signal as a write address signal until a following external write operation;
a refresh circuit to generate refresh operation requests and to generate a refresh address signal for refreshing the memory cells of the memory cell array during a refresh operation;
a control circuit to generate an internal control signal, the internal control signal comprising a read selecting signal generated during a pulsed read operation, a write selecting signal generated during a pulsed write operation, and a refresh selecting signal generated during a refresh operation, and to generate a refresh blocking signal to disable refresh operation requests during an access subinterval of each external read/write operation during which the device performs the pulsed read or write operation;
an address multiplexer to select one of the internal address signal, the write address signal and the refresh address signal as an array address signal, based on the internal control signal;
row and column decoders to address one or more cells of the memory cell array based on the array address signal;
a data input register to store data input information received during an external write operation until a following external write operation;
a comparator to compare the internal address signal with the write address signal during a read operation;
and
a data output multiplexer to select either the data input information stored in the data input register, or data output from one or more cells of the memory cell array, based on an output signal of the comparator during a read operation, wherein the data output multiplexer selects the data input information stored in the data input register when the internal address signal matches the write address signal, and otherwise selects the data from the memory cells.

7 more elements

A method of operating a semiconductor memory device having a refresh-type memory cell array and a refresh circuit, the method comprising:

when a current write operation is externally requested, initiating a pulsed write operation in order to write data previously stored in a data input register to a cell array address previously stored in a write address register, storing a write address received during the current write operation to the write address register, and storing data received during the current write operation to the data input register;
when a read operation is externally requested, initiating a pulsed read operation of the memory cell array at an array address corresponding to a read address received during the read operation, comparing the read address to the address stored in the write address register, and when the addresses match, selecting the data stored in the data input register for output, otherwise selecting the data returned from the pulsed read operation for output;
when a refresh operation request precedes an external read/write operation request, initiating a pulsed refresh operation and completing that pulsed refresh operation before completing a pulsed read/write operation for the external read/write operation request;
when a refresh operation request occurs during a pulsed read/write operation, initiating a pulsed refresh operation after completing the pulsed read/write operation;
and
when a refresh operation request occurs during an external read/write operation but after completion of the pulsed read/write operation initiated during that external operation, initiating a pulsed refresh operation at the time of the refresh request.

3 more elements

A semiconductor memory device having a refresh-type memory cell array and a refresh circuit, the device comprising:

a data input register;
a write address register;
write circuit means for initiating a pulsed write operation having a set duration during an externally-requested current write operation, in order to write data previously stored in the data input register to a cell array address previously stored in the write address register, storing the write address received during the current write operation to the write address register, and storing data received during the current write operation to the data input register;
read circuit means for initiating a pulsed read operation having a set duration during an eternally-requested read operation, comparing the read address for the read operation to the address stored in the write address register, and when the addresses match, selecting the data stored in the data input register, otherwise selecting the data stored at the cell array address corresponding to the read address;
and
control circuit means for generating pulsed write operation, pulsed read operation, and pulsed refresh operation timing signals, and for disabling refresh operation requests from the refresh circuit during pulsed write operations and pulsed read operations.

3 more elements

A semiconductor memory device having a refresh-type memory cell array and a refresh circuit, the device comprising:

a write address register to store a write address from a current external write operation until a pulsed write operation occurring sometime after the end of the current external write operation;
a data input register to store input data from the current external write operation until the pulsed write operation occurs;
a read/write pulse control circuit to generate timing control signals for pulsed read operations, pulsed write operations, and pulsed refresh operations, and to generate a refresh operation disabling signal during pulsed read and write operations, the timing control signals for a pulsed write operation initiating a late write of the input data stored in the data input register at a memory cell array address corresponding to the write address stored in the write address register;
an address multiplexer to select one of a refresh address, an external input address, and the write address from the write address register as the input address to the memory cell array in response to the timing control signals generated by the read/write pulse control circuit;
an address comparator to compare the external input address with the address stored in the write address register;
and
a data output multiplexer to select for output from the device, during an external read operation, one of the input data stored in the data input register and data read from the memory cell array address corresponding to the external input address, the selection responsive to the comparison performed by the address comparator.

4 more elements

Dependencies are inferred from the claim text.