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US 6,275,433 B1Granted
Four transistor SRAM cell with improved read access
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A memory cell comprises first and second output nodes, a first transistor coupled between a first power supply node and the first output node, a first load coupled between the first output node and a second power supply node, a second load coupled between the first power supply node and the second output node, and a second transistor coupled between the second output node and the second power supply node. A gate terminal of the first transistor is coupled to the second output node, and a gate terminal of the second transistor is coupled to the first output node.
Claims28
A memory cell, comprising:
- first and second output nodes;
- a first transistor coupled between a first power supply node and the first output node;
- a first load coupled between the first output node and a second power supply node;
- a second load coupled between the first power supply node and the second output node;
- and
- a second transistor coupled between the second output node and the second power supply node,
- a gate terminal of the first transistor being coupled to the second output node, and a gate terminal of the second transistor being coupled to the first output node.
4 more elements
A sense amplifier, comprising:
- first and second output nodes;
- a first transistor coupled between a first power supply node and the first output node;
- a second transistor coupled between the first output node and a second power supply node, the second transistor having a gate terminal coupled to a first bit line;
- a third transistor coupled between the first power supply node and the second output node;
- a fourth transistor coupled between the first power supply node and the second output node, the fourth transistor having a gate terminal coupled to a clock signal line;
- and
- a fifth transistor coupled between the second output node and the second power supply node, the fifth transistor having a gate terminal coupled to a second bit line,
- the sense amplifier adapted to provide first and second output signals at the first and second output nodes, respectively, in response to signals on the first and second bit lines and a clock signal on the clock signal line.
5 more elements
A sense amplifier, comprising:
- first and second output nodes;
- a first load coupled between a first power supply node and the first output node;
- a second load coupled between the first power supply node and the second output node;
- a first input transistor coupled between the first output node and a second power supply node, the first in put transistor having a gate terminal coupled to a first bit line;
- a second input transistor coupled between the second output node and the second power supply node, the second input transistor having a gate terminal coupled to a second bit line;
- and
- a pre-charge transistor coupled between the first power supply node and the second output node, the pre-charge transistor having a gate terminal coupled to a clock signal line, the pre-charge transistor adapted to couple the second output node to the first power supply node during a first phase of a clock signal on the clock signal line.
4 more elements
A memory cell sense circuit, comprising:
- a sense amplifier, having:
- first and second sense amplifier output nodes;
- a sense amplifier pre-charge transistor coupled between a first power supply node and the second sense amplifier output node, the pre-charge transistor having a gate terminal coupled to a clock signal line, the pre-charge transistor adapted to couple the second sense amplifier output node to the first power supply node during a first phase of a first clock signal on the clock signal line;
- a first input transistor coupled between the first sense amplifier output node and a sense amplifier activating node, the first input transistor having a gate terminal coupled to a first bit line;
- a second input transistor coupled between the second sense amplifier output node and the sense amplifier activating node, the second input transistor having a gate terminal coupled to a second bit line;
- and
- a sense amplifier activating transistor coupled between the second amplifier activating node and a second power supply node, the sense amplifier activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors to the second power supply node during a second phase of the first clock signal on the clock signal line;
- a first driver circuit, having:
- a first driver output node;
- a first driver pre-charge transistor coupled between the first power supply node and the first driver output node, the first driver pre-charge transistor having a gate terminal coupled to the clock signal line and adapted to couple the first driver output node to the first power supply node during a first phase of a second clock signal on the clock signal line;
- a first input transistor coupled between the first power supply node and a first driver activating node, the first input transistor of the first driver having a gate terminal coupled to the first sense amplifier output node;
- a second input transistor coupled between the first driver output node and the first driver activating node, the second input transistor of the first driver having a gate terminal coupled to the second sense amplifier output node;
- and
- a first driver activating transistor coupled between the first driver activating node and the second power supply node, the first driver activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors of the first driver to the second power supply node during a second phase of the second clock signal in the clock signal line;
- a second driver circuit, having,
- a second driver output node;
- a second driver pre-charge transistor coupled between the first power supply node and the second driver output node, the second driver pre-charge transistor having a gate terminal coupled to the clock signal line and adapted to couple the second driver output node to the first power supply node during a first phase of the second clock signal on the clock signal line;
- a first input transistor coupled between the first power supply node and a second driver activating node, the first input transistor of the second driver having a gate terminal coupled to the second sense amplifier output node;
- a second input transistor coupled between the second driver output node and the second driver activating node, the second input transistor of the second driver having a gate terminal coupled to the first sense amplifier output node;
- and
- a second driver activating transistor coupled between the second driver activating node and the second power supply node, the second driver activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors of the second driver to the second power supply node during a second phase of the second clock signal on the clock signal line;
- and
- a driver output circuit, having:
- a driver circuit output node;
- a driver circuit pre-charge transistor coupled between the first power supply node and the driver circuit output node, the driver circuit pre-charge transistor having a gate terminal coupled to the clock signal line and adapted to couple the driver circuit output node to the first power supply node during a first phase of a third clock signal on the clock signal line;
- a first input transistor coupled between the first power supply node and a driver circuit activating node, the first input transistor of the driver circuit having a gate terminal coupled to the second driver output node;
- a second input transistor coupled between the driver circuit output node and the driver circuit activating node, the second input transistor of the driver circuit having a gate terminal coupled to the first driver output node;
- and
- a driver circuit activating transistor coupled between the driver circuit activating node and the second power supply node, the driver circuit activating transistor having a gate terminal coupled to the clock signal line and adapted to couple the first and second input transistors of the driver circuit to the second power supply node during a second phase of the third clock signal on the clock signal line.
26 more elements
A memory cell sense circuit, comprising:
- a sense amplifier coupled to first and second bit lines and having first and second sense amplifier output nodes;
- a first driver circuit coupled to the first and second sense amplifier output nodes and having a first driver output node;
- a second driver circuit coupled to the first and second sense amplifier output nodes and having a second driver output node;
- and
- an output driver circuit coupled to the first and second driver output nodes and having an output driver output node,
- the sense amplifier having a pre-charge transistor coupled to the second sense amplifier output node and adapted to pre-charge the second sense amplifier output node to approximately a first power supply potential, and
- each of the first driver circuit, the second driver circuit and the output driver circuit having a pre-charge transistor coupled to its respective output node and adapted to pre-charge its respective output node to approximately the first power supply potential.
4 more elements
Dependencies are inferred from the claim text.