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AssigneeFujitsu Limited
InventorsKazumi Kojima, Yasushige Ogawa
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In a semiconductor memory device which is intended to lower the power consumption and raise the operation speed without increasing the circuit scale to meet trends toward the larger capacity, higher speed and, at the same time, the lower power voltage design, the precharge circuit Pre3 has its bit line shorting section formed of transistors TN1A and TN1B in series connection and its bit line voltage holding circuit formed of transistors TN2A and TN2B connected in series between the node of the transistors TN1A and TN1B and a precharge voltage VPR source, with the transistors TN1A and TN2A and the TN1B and TN2B being controlled by precharge signals BRS0 and BRS1, respectively. One of the precharge signals BRS0 and BRS1 is preset active since the former precharge operation cycle, the other precharge signal is activated to start the shorting operation of a bit line pair /BL-BL, and the preset precharge signal is deactivated to end the shorting operation.
A semiconductor memory device having, for each bit line pair, a bit line pair shorting circuit which shorts the bit line pair, and a bit line voltage holding circuit which holds the voltage of bit lines at a predetermined voltage,
A semiconductor memory device having, for each bit line pair, a bit line pair shorting circuit which shorts the bit line pair, and a bit line voltage holding circuit which holds the voltage of the bit lines at a predetermined voltage,
A method of controlling a semiconductor memory device for shorting each bit line pair and holding the voltage of the bit lines at a predetermined voltage,
Dependencies are inferred from the claim text.