Memory device and equalizing circuit for memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYong-cheol Bae, Jung-hwa Lee
Life of this patent
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Abstract
An input and output line equalizing circuit for connection to a pair of input and output lines of a memory device. The equalizing circuit includes an equalization control circuit providing at an output a precharge signal, and an equalizing unit connected to the input and output lines. The equalizing unit responding to receipt of a precharge signal from the equalization control circuit to maintain the pair of input and output lines at the same voltage level. The equalizing control circuit includes a first transmission gate and a second transmission gate.
Claims7
An equalizing circuit for connection to a pair of input and output lines of a memory device, the equalizing circuit comprising:
- an equalization control circuit including a first terminal for receiving a first equalization signal, a second terminal for receiving a second, different equalization signal, an input terminal for receiving a precharge signal, and an output terminal for providing a precharge signal in response to activation of the first or second equalization signal;
- and
- an equalizing unit having a control terminal coupled to the output terminal of the equalization control circuit, said equalizing unit being connected to the pair of input and output lines, for maintaining the pair of input and output lines at the same voltage level.
A memory device including first and second memory blocks and a pair of input and output lines which are shared by the first and second memory blocks, the memory device comprising:
- first and second bitline precharge circuits for precharging to a predetermined voltage a first and a second pair of bitlines associated with the first and second memory blocks respectively;
- first and second bitline sense amplifiers associated respectively with the first and second pair of bitlines for sensing and amplifying data on the pairs of bitlines;
- a first and a second block selection switch associated respectively with said first and second memory blocks, and a first and a second column selection gate associated respectively with said first and second memory blocks for connecting a selected pair of bitlines of a selected memory block to the pair of input and output lines;
- a first equalizing circuit coupled to the pair of input and output lines at a first location, wherein power to said first equalizing circuit is provided by a back-bias of an external supply voltage;
- and
- a second equalizing circuit coupled to the pair of input and output lines at a second location spaced apart from said first location.
Dependencies are inferred from the claim text.