Memory-embedded semiconductor integrated circuit device and method for testing same

A memory-embedded semiconductor integrated circuit device comprising:

• a logic part provided on a semiconductor substrate;
• a memory macro provided on said semiconductor substrate to be consolidated with said logic part;
• an input terminal for inputting an input signal;
• a timing adjusting circuit for incorporating and outputting said input signal, which is inputted via said input terminal, in synchronism with a clock signal, or for immediately incorporating and outputting said input signal, in accordance with a control signal;
• a generator for generating a signal, which serves to operate said memory macro, on the basis of said input signal which is fed via said timing adjusting circuit;
• and
• an output terminal for receiving an output of said memory macro, which has been operated by said signal, to output said output of said memory macro to the outside.

A method for testing a memory-embedded semiconductor integrated circuit device comprising:

• a logic part provided on a semiconductor substrate;
• a memory macro provided on said semiconductor substrate to be consolidated with said logic part;
• a test input terminal for inputting a test input signal comprising a test command or test data;
• a test circuit including a test signal generator for generating an output switching signal and a test signal, which serves to carry out a test operation of said memory macro, on the basis of said test input signal, and a switching circuit for selectively outputting one of an output of said memory macro, which has been test-operated by said test signal, and said test input signal in accordance with said output switching signal;
• and a test output terminal for receiving an output of said switching circuit to output said output of said switching circuit to the outside, said method comprising the steps of:
• inputting said test command to said test input terminal, and activating said output switching signal;
• inputting said test data to said test input terminal;
• and
• receiving data, which are outputted from said switching circuit, via said test output terminal to compare the received data with said test data.

A method for testing a memory-embedded semiconductor integrated circuit device comprising:

• a logic part provided on a semiconductor substrate;
• a memory macro provided on said semiconductor substrate to be consolidated with said logic part;
• a test input terminal for inputting a test input signal comprising a test command or test data;
• a test circuit including a timing adjusting circuit for incorporating and outputting said test input signal, which is inputted via said test input terminal, in synchronism with a clock signal, or for immediately incorporating and outputting said test input signal, in accordance with a control signal, and a test signal generator for generating a test signal, which serves to operate said memory macro, on the basis of said test input signal which is fed via said timing adjusting circuit;
• and a test output terminal for receiving an output of said memory macro, which has been operated by said test signal, to output said output of said memory macro to the outside, said method comprising the step of:
• changing a timing in inputting said test data to said test input terminal, to repeat the input of said test data to said test input terminal while said control signal is in an inactive state.