Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test

A method of testing a silicon-on-insulator (SOI) static random access memory (SRAM), the method comprising:

• (a) initializing each of a plurality of memory cells in a memory array to a first state;
• (b) accessing the plurality of memory cells in a predetermined sequence, including, for each memory cell:
• (i) setting the memory cell to a second, opposite state for that memory cell;
• and
• (ii) disturbing the memory cell after setting the memory cell to the second state;
• and
• (c) after accessing the plurality of memory cells, determining the current state of each memory cell to confirm whether the memory cell is still in the second state for that memory cell.

A method of testing a silicon-on-insulator (SOI) static random access memory (SRAM), the method comprising:

• (a) initializing each memory cell in a memory array to a zero logic state;
• (b) after initializing each memory cell to the zero logic state, waiting for completion of a first BIST scan operation;
• (c) accessing each memory cell in the memory array a first time by sequentially setting each memory cell to a one logic state and in an immediately subsequent memory access cycle reading the memory cell;
• (d) after accessing each memory cell in the memory array the first time, determining the current state of each memory cell a first time to confirm whether the memory cell is still in the one logic state;
• (e) after determining the current state of each memory cell the first time, initializing each memory cell in the memory array to a one logic state;
• (f) after initializing each memory cell to the one logic state, waiting for completion of a second BIST scan operation;
• (g) accessing each memory cell in the memory array a second time by sequentially setting each memory cell to the zero logic state and in an immediately subsequent memory access cycle reading the memory cell;
• (h) after accessing each memory cell in the memory array the second time, determining the current state of each memory cell a second time to confirm whether the memory cell is still in the zero logic state;
• and
• (i) indicating a test fail if, during determining the current state of each memory cell the first time, any memory cell is determined to be in the zero logic state, or if, during determining the current state of each memory cell the second time, any memory cell is determined to be in the one logic state.