Row redundancy for content addressable memory

The CAM device of claim 17, further comprising:

• a one-shot circuit configured to generate a one-shot signal in response to a reset signal;
• and
• a shift register circuit coupled to receive the one-shot signal and coupled to the first and second spare address decoders.
• 20.The CAM device of claim 19, wherein:
• the first main CAM array comprises a plurality of main word lines each coupled to one of the plurality of rows of CAM cells;
• and
• the first replacement means comprises a plurality of latch circuits each having a data input coupled to one of the main word lines, an output coupled to one of the main match lines, and a clock input responsive to a first clock signal.

A content addressable memory (CAM) device comprising:

• a main CAM array having a plurality of rows of CAM cells each coupled to a main match line;
• main match line control circuitry coupled to the main match lines of the main CAM array;
• a spare row of CAM cells coupled to a spare match line;
• and
• a spare match line control circuit coupled to the spare match line of the spare row of CAM cells.

A method of replacing a defective row of content addressable memory (CAM) cells, comprising:

• asserting a word line of the defective row to a predetermined logic state;
• asserting a match line of the defective row to a mismatch state state of the word line;
• and
• enabling a spare row of CAM cells coupled to a spare match line to replace the defective row of CAM cells.