Semiconductor device having memory cell part and transfer circuit
AssigneeOki Electric Industry Co., Ltd.
InventorsMikio Fujita, Hisaki Ishida
Life of this patent
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Abstract
A semiconductor device includes a memory cell part which has data input terminals and which stores data received at the data input terminals and a data bus which is supplied with data. The semiconductor device also includes a transfer circuit which is coupled between the data bus and the data input terminals and which transfers the data from the data bus to the data input terminals in response to a transfer selection signal. The semiconductor device also includes a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.
Claims17
A semiconductor device comprising:
- a memory cell part which has data input terminals and which stores data received at the data input terminals;
- a first data bus which is supplied with a bit processing signal comprised of a plurality of bits;
- a second data bus which is supplied with a bit selection signal comprised of a plurality of bits;
- a selector which is coupled to said first and second data buses and which transfers either the bit processing signal or the bit selection signal in response to a bus selection signal;
- a transfer circuit which is coupled between said selector and the data input terminals and which transfers a signal from said selector to the data input terminals in response to a transfer selection signal;
- and
- a transfer control circuit which receives the bit selection signal and outputs the transfer selection signal.
A semiconductor device as set forth 3, wherein said transfer control circuit receives a write signal and a bit processing signal, said transfer control circuit outputs the transfer selection signal having the bits which are set to the first voltage levels when the write signal is in the first voltage level and outputs the transfer selection signal having the bits each of which is set to a predetermined voltage level when the write signal is in the second voltage level and the bit processing signal is in the first voltage level.
A semiconductor device comprising:
- a memory cell part which has data input terminals and which stores data received at the data input terminals;
- a data bus which is applied to a bit processing signal having a plurality of bits;
- a bit selection signal bus which is applied to a bit selection signal having a plurality of bits;
- a transfer circuit which is coupled between said data bus and the data input terminals and which transfers the bit processing signal from said data bus to the data input terminals in response to a transfer selection signal;
- and
- a transfer control circuit which receives the bit selection signal and outputs the transfer selection signal.
A semiconductor device comprising;
- a memory cell part which has data input terminals and which stores data received at the data input terminals;
- a data bus which is supplied with data;
- a plurality of buffers, each of which has an input node coupled to said data bus, an output node coupled to a corresponding data input terminal of the data input terminals and a control terminal receiving a transfer selection signal, and each of which transfers data received at the input node thereof to the corresponding data input terminal of the data input terminals when a corresponding control terminal of the buffers receives a first voltage level, and each of the output nodes of the buffers being made into a high impedance state when a corresponding control terminal of the buffers receives a second voltage level;
- and
- a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.
Dependencies are inferred from the claim text.