Pulse generator circuit, particularly for non-volatile memories
AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
Life of this patent
Estimating the term…
Abstract
A pulse generator circuit for non-volatile memories, is disclosed, including a circuit for determining the instant at which a pulse for incrementing a counter of the memory is generated and generating an increment pulse duration start signal; a circuit for determining the minimum amplitude of the increment pulse and generating an increment pulse duration end signal; a first logic circuit for enabling the generation of the increment pulse based upon the increment pulse duration start and end signals; and an increment pulse generation circuit for generating or suppressing the increment pulse of the counter of the memory, based upon the current condition of the memory.
Claims30
A pulse generator circuit, particularly for non-volatile memories, comprising:
- means for determining the instant at which a pulse for incrementing a counter of the memory is generated, said means being adapted to generate an increment Pulse duration start signal;
- means for determining a minimum amplitude of said increment pulse which are connected to the output of said means for determining the instant at which the increment pulse is generated and are adapted to generate an increment pulse duration end signal;
- first logic means for enabling the generation of said increment pulse which receive in input said increment pulse duration start and increment pulse duration end signals;
- timing means for generating one or more control signal;
- and
- increment pulse generation means which are cascade-connected to said first logic means and are adapted to selectively generate said increment pulse of at least one address counter of the memory as a function of the one or more control signals received from said timing means, said control signals being correlated to the current condition of said memory.
A method for generating increment pulses, particularly for non-volatile memories, comprising the steps of:
- determining an instant in which the generation of an increment pulse begins, said instant being closely correlated to the read cycle of the memory;
- determining a minimum allowed duration of said increment pulse;
- generating said increment pulse following the occurrence of enable conditions, according to a protocol of said memory, to increment at least one address counter for which said increment signal is intended and by which address values are generated.
Timing circuitry for controlling at least one address counter of a random access memory device, comprising:
- a first circuit for receiving at least one control signal and generating a pulse signal based upon the at least one control signal, the first circuit being a self-timed circuit;
- and
- a second circuit for receiving the pulse signal, selectively suppressing the pulse signal based upon a present condition of the random access memory device, and applying the pulse signal to a clock input of the at least one address counter.
A method of clocking at least one address counter of a random access memory device, comprising:
- receiving at least one control signal during a memory access operation and generating a pulse signal responsive to the at least one control signal and having a predetermined pulse duration;
- selectively suppressing the pulse signal based upon a present condition of the random access memory device;
- and
- applying the pulse signal to the at least one address counter.
Dependencies are inferred from the claim text.