Multiple byte channel hot electron programming using ramped gate and source bias voltage

A method of programming a memory device, comprising multiple memory cells each having a control gate and a floating gate formed over a substrate and each having a source and a drain formed in a well region formed in the substrate, wherein the drains have a common drain terminal and wherein the sources have a common source terminal and wherein the well regions have a common terminal, the method comprising:

• selecting at least one bank of memory cells;
• applying a voltage to the common drain terminal;
• applying a time varying voltage to the control gates of memory cells that are to be programmed, wherein the voltage applied to the control gates of memory cells that are to be programmed is increased until a predetermined programming voltage is reached at which time the voltage applied to the control gates of memory cells that are to be programmed is removed;
• applying a bias voltage to the common well terminal;
• and
• applying a bias voltage to the common source terminal, wherein the bias voltage applied to the common well terminal and the bias voltage applied to the common source terminal in combination with the voltage applied to the control gates of the memory cells that are to be programmed substantially prevents background leakage current during application of the voltage applied to the control gates and maintains programming speed.

A memory device, comprising:

• multiple banks, each bank having multiple memory cells each cell having a control gate and a floating gate formed over a substrate and each having a source and a drain formed in the substrate, wherein the drains have a common drain terminal and wherein the sources have a common source terminal;
• and
• programming circuitry that selects at least one bank, that applies a voltage to the common drain terminal, that applies a time varying voltage to control gates of memory cells that are to be programmed, wherein the programming circuitry increases the voltage applied to the control gates of the memory cells that are to be programmed until a predetermined programming voltage is reached at which time the programming circuitry removes the voltage applied to the control gates of memory cells that are to be programmed;
• and wherein the programming circuitry applies a bias voltage to the common source terminal wherein the bias voltage applied to the common source terminal by the programming circuitry in combination with the voltage applied to the control gates of the memory cells that are to be programmed substantially prevents background leakage current and maintains programming speed during application of the voltage applied to the control gates.