Method and apparatus for terminating direct memory access transfers from system memory to a video device
AssigneeIntel Corporation
InventorsNilesh V. Shah, Andrew E. Roedel, Cliff D. Hall
Life of this patent
Estimating the term…
Abstract
An embodiment of a method for terminating direct memory access transfers from system memory to a video device includes completing a current byte transfer from a graphics controller to a video device and then refraining from initiating any further write cycles associated with a DMA transfer to the video device. The graphics controller then allows uninterrupted or atomic read and write cycles to the video device. The graphics controller also completes any current read cycles on a system bus that had previously been initiated. The graphics controller then resets its DMA engine and invalidates all information in a first-in, first-out (FIFO) storage buffer.
Claims19
A method, comprising:
- halting at least one pending direct memory access write cycle to a video device;
- allowing an uninterrupted read and write access to the video device;
- completing a current direct memory access read cycle from a memory device;
- and
- resetting a direct memory access register and a temporary storage location.
A method, comprising:
- setting a hold data burst bit in a graphics controller;
- completing a current information transfer associated with a direct memory access from the graphics controller to a video device if the current information transfer is in progress;
- refraining from initiating a further information transfer associated with a direct memory access from the graphics controller to the video device while the hold data burst bit is set;
- setting an abort bit in the graphics controller;
- setting an abort pending bit in the graphics controller in response to the setting of the abort bit;
- completing a current direct memory access read cycle from a memory device to the graphics controller;
- invalidating a contents of a direct memory access storage buffer in the graphics controller in response to the setting of the abort pending bit;
- resetting at least one direct memory access request register in the graphics device in response to the setting of the abort pending bit;
- clearing the abort pending bit;
- and
- clearing the abort bit and the hold data burst bit.
An apparatus, comprising:
- a direct memory access unit to perform at least one memory read cycle from a memory device and at least one write cycle to a video device;
- a first storage location to indicate to a video device interface circuit to halt at least one pending direct memory access write cycle to the video device when the first storage location contains a first predetermined value;
- and
- a second storage location to indicate to a system bus interface circuit to complete at least one current direct memory access read cycle when the second storage location contains a second predetermined value, the video device interface circuit further to reset the direct memory access unit in response to the second storage location containing the second predetermined value.
A system, comprising:
- a memory device coupled to a system bus;
- a video device couple to a video bus;
- a graphics controller coupled to the system bus and further coupled to the video bus, the graphics controller including
- a direct memory access unit to perform at least one memory read cycle from the memory device and at least one write cycle to the video device;
- a first storage location to indicate to a video device interface circuit to halt at least one pending direct memory access write cycle to the video device when the first storage location contains a first predetermined value;
- and
- a second storage location to indicate to a system bus interface circuit to complete at least one current direct memory access read cycle when the second storage location contains a second predetermined value, the video device interface circuit further to reset the direct memory access unit in response to the second storage location containing the second predetermined value.
Dependencies are inferred from the claim text.