Circuit and method for controlling an output of a ring oscillator
AssigneeCypress Semiconductor Corporation
InventorsKhaldoon Abugharbieh, Sung-Ki Min
Life of this patent
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Abstract
A circuit and method configured to generate a variable impedance. The circuit may comprise a voltage controlled resistor configured to generate the variable impedance in response to (i) a first transistor configured to receive a first control signal and (ii) a bias transistor configured to receive a bias signal. In one example, the variable impedance may be generated in further response to a clamp transistor.
Claims20
A circuit configured to generate a output signal having a frequency comprising:
- a voltage controlled resistor configured to generate a variable impedance in response to (i) a first transistor configured to receive a control signal and (ii) a bias transistor configured to receive a bias signal, wherein said bias signal causes said bias transistor to remain in a linear region and said bias transistor is weak compared to said first transistor and is configured to improve said variable impedance when said first transistor is saturated.
A method configured to generate a variable impedance output signal comprising the steps of:
- (a) controlling a first device;
- (b) controlling a bias device, wherein said bias device is weaker than said first device;
- and
- (c) generating said variable impedance output signal in response to (i) a control signal and (ii) a bias signal, wherein step (c) comprises causing step (a) to remain in a linear region and step (b) to improve said variable impedance output signal when said first device is saturated.
A circuit configured to generate a variable impedance output signal comprising:
- a voltage controlled resistor configured to generate said variable impedance output signal in response to (i) a first transistor configured to receive a control signal, (ii) a bias transistor configured to receive a bias signal, wherein said bias transistor is weaker than said first transistor and (iii) a clamp transistor, wherein said bias signal causes said bias transistor to remain in a linear region and said bias transistor is configured to improve said variable impedance output signal when said first transistor is saturated and said clamp transistor is cut-off.
A circuit configured to generate an output signal having a frequency comprising:
- a voltage controlled resistor configured to generate a variable impedance in response to (i) a first transistor configured to receive a control signal and (ii) a bias transistor configured to receive a bias signal, wherein said bias signal causes said bias transistor to remain in a linear region and said bias transistor is between 1% to 30% as strong as said first transistor and is configured to improve said variable impedance when said first transistor is saturated.
An apparatus configured to generate an output signal having a frequency comprising:
- means for generating a control signal;
- means for generating a bias signal, wherein said bias signal generating means is weaker than said control signal generating means;
- and
- means for generating a variable impedance in response to (i) said control signal and (ii) said bias signal, wherein (i) said bias signal causes said control signal generating means to remain in a linear region and (ii) said bias signal generating means is weaker than said control signal generating means and is configured to improve said variable impedance when said control signal generating means is saturated.
Dependencies are inferred from the claim text.