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US 6,275,091 B1Granted
Clock signal control circuit and method and synchronous delay circuit
AssigneeNEC Corporation
InventorTakanori Saeki
Life of this patent
Estimating the term…
Abstract
A clock signal control circuit that permits the on-chip circuit dimensional size to be reduced is provided. The clock signal control circuit includes a plurality of amplifier circuit elements amplifying the input clock signal and a plurality of switching elements switching the passage of the clock signal on and off, wherein the plurality of amplifier circuit elements and the plurality of switching elements are connected in such a way that the amplifier circuit elements may be connected in a series fashion when they are operational. Selecting those switching elements that are switched on causes the amplifier circuit elements to be switched so that their series-fashion connection can be reversed to allow the clock signal to travel in the backward direction.
Claims19
A clock signal control method for a delay circuit, comprising the steps of:
- providing a delay circuit comprising a plurality of amplifier circuit elements each amplifying a clock signal applied thereto;
- and a plurality of switching elements each switching passage of the clock signal on and off,
- connecting said plurality of amplifier circuit elements in a series fashion through said switching elements that are switched on;
- and
- selecting said switching elements that are switched on, thereby allowing a direction in which the clock signal is traveling through said plurality of amplifier circuit elements connected in a series fashion to be switched between a forward direction and a backward direction.
2 more elements
A clock signal control circuit comprising:
- a plurality of amplifier circuit elements each amplifying a clock signal applied thereto;
- and
- a plurality of switching elements each switching passage of the clock signal on and off, wherein
- said plurality of amplifier circuit elements are connected in a series fashion through said switching elements that are switched on;
- and
- said switching elements that are switched on are selected, thereby allowing a direction in which said clock signal is traveling through said plurality of amplifier circuit elements to be switched between a forward direction and a backward direction.
3 more elements
A delay circuit comprising:
- (a) a first group of switching elements connected in series between a first input terminal and a first output terminal and including switching elements alternately controlled to be switched on and off by a control signal, or by said control signal and a complementary signal thereof for switching passage of a clock signal on and off;
- (b) a second group of switching elements connected in series between a second input terminal and a second output terminal and including switching elements alternately controlled to be switched on and off by the control signal, or by said control signal the complementary signal thereof for switching passage of the clock signal on and off;
- and
- (c) a plurality of amplifier circuit elements connected between the respective junction nodes of the adjacent switching elements of the first group and the respective corresponding junction nodes of the adjacent switching elements of the second group in such a way that one of said plurality amplifier circuit elements is connected forwardly or reversely alternately one to another,
- (d) wherein said plurality of amplifier circuit elements are connected in a series fashion through said switching elements that are switched on, and are shared by respective signal paths (i) between said first input terminal and said first output terminal and (ii) between said second input terminal and said second output terminal, and
- (e) wherein a direction in which the clock signal is traveling along said respective signal paths may be switched between a first direction from said first input terminal toward said first output terminal and a second direction from said second input terminal toward said second output terminal, by selecting said switching elements that are switched on.
3 more elements
A delay circuit comprising:
- (a) a first group of switching elements including a first type of switching elements and a second type of switching elements controlled to be switched on and off by a control signal and a complementary signal thereof, said switching elements of the first type and said switching elements of the second type being connected in series from a first input terminal toward a first output terminal such that each switching element of one type is followed by each switching element of the other type in an alternate manner;
- (b) a second group of switching elements including a second type of switching elements and a first type of switching elements controlled to be switched on and off by the control signal and the complementary signal thereof, said switching elements of the second type and said switching elements of the first type being connected in series from a second input terminal located on the side of said first input terminal toward a second output terminal located on the side of said first output terminal such that each switching element of one type is followed by each switching element of the other type in an alternate manner;
- and
- (c) a plurality of amplifier circuit elements connected between each respective junction node of the adjacent switching elements in said first group of switching elements and each respective corresponding junction node of the adjacent switching elements in the second group of switching elements, each alternate one of said plurality of amplifier circuit elements having its input terminal and its output terminal connected (i) between said each respective junction node of the adjacent switching elements in said first group of switching element and said each respective junction node of the adjacent switching elements in said second group of switching elements and (ii) between said each respective junction node of the adjacent switching elements in said second group of switching elements and said each respective junction node of the adjacent switching elements in said first group of switching elements, respectively.
1 more element
A delay circuit comprising:
- (a) a first group of switching elements including a first type of switching elements and a second type of switching elements controlled to be switched on and off by a control signal when it is active, each alternate one of said switching elements of the first type and said switching elements of the second type being connected in series between a first input terminal and a first output terminal along this direction;
- (b) a second group of switching elements including a second type of switching elements and a first type of switching elements controlled to be switched on and off, respectively, by the control signal when it is inactive, each alternate one of said switching elements of the second type and said switching elements of the first type being connected in series between a second input terminal located on the side of said first output terminal and a second output terminal located on the side of said first input terminal along this direction;
- and
- (c) a plurality of amplifier circuit elements connected between each respective junction node of the adjacent switching elements in said first group of switching elements and each respective corresponding junction node of the adjacent switching elements in the second group of switching elements, each alternate one of said plurality of amplifier circuit elements having its input terminal and its output terminal connected in an alternate fashion, (i) between said each respective junction node of the adjacent switching elements in said first group of switching element and said each respective junction node of the adjacent switching elements in said second group of switching elements and (ii) between said each respective junction node of the adjacent switching elements in said second group of switching elements and said each respective junction node of the adjacent switching elements in said first group of switching elements, respectively.
1 more element
A delay circuit comprising:
- (a) a first group of switching elements including P-type channel MOS transistors and N-type channel MOS transistors connected in series between a first input terminal and a first output terminal in such a way that each alternate one of the transistors of one type is followed by each alternate one of the transistors of the other type, and controlled so that the transistors of the one type may be turned off when the transistors of the other type are turned on, in accordance with a predetermined value of a control signal;
- (b) a second group of switching elements including P-type channel MOS transistors and N-type channel MOS transistors connected in series between a second input terminal located on the side of said first output terminal and a second output terminal located on the side of said first input terminal in such a way that each alternate one of the transistors of one type is followed by each alternate one of the transistors of the other type, and control led so that the transistors of the one type may be turned off when the transistors of the other type are turned on, in accordance with a predetermined value of a complementary signal of said control signal that is reversed by an inverter;
- and
- (c) a plurality of inverter circuits connected between each respective junction node of the adjacent transistors in said first group of switching elements and each respective corresponding junction node of the adjacent transistors in the second group of switching elements, each alternate one of said plurality of inverter circuits having its input terminal and its output terminal connected, in an alternate fashion, (i) between said each respective junction node of the adjacent transistors in said first group of switching element and said each respective junction node of the adjacent transistors in said second group of switching elements and (ii) between said each respective junction node of the adjacent transistors in said second group of switching elements and said each respective junction node of the adjacent transistors in said first group of switching elements, respectively.
1 more element
Dependencies are inferred from the claim text.