US 6,275,086 B1Granted

Clock signal generator for an integrated circuit

AssigneeFujitsu Limited

InventorsHiroko Douchi, Hiroyoshi Tomita

Life of this patent

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Abstract

A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers. A logic gate receives the first enable signal and the first internal clock signal and controls the output of the first internal clock signal.

Claims15

Dependent claims

A semiconductor integrated circuit comprising:

a plurality of clock signal input circuits, including a first clock signal input circuit and a second clock signal input circuit, each receiving a respective one of a plurality of external clock signals and generating a respective one of a plurality of internal clock signals;
an external control signal input circuit for receiving an external control signal and generating an internal control signal;
and
an output control circuit for receiving the internal control signal and controlling the output of the internal clock signals, wherein the output control circuit includes:
a latch circuit connected to the external control signal input circuit and the first clock signal input circuit, where the latch circuit latches the internal control signal in response to a first internal clock signal generated by the first clock signal input circuit;
a first enable signal generating circuit connected to the latch circuit and the first clock signal input circuit, wherein the first enable signal generating circuit holds the latched internal control signal in response to the first internal clock signal and generates a first enable signal;
a gate circuit connected to the first enable signal generating circuit and the first clock signal input circuit, wherein the gate circuit controls the output of the first internal clock signal in accordance with the first enable signal;
and
a second enable signal generating circuit connected to the first enable signal generating circuit and the second clock signal input circuit, wherein the second enable signal generating circuit holds the first enable signal in response to the first internal clock signal and generates a second enable signal for selectively activating and deactivating the second clock signal input circuit.

6 more elements

A semiconductor integrated circuit comprising:

a plurality of clock signal input circuits, including a first clock signal input circuit and a second clock signal input circuit, each receiving a respective one of a plurality of external clock signals and generating a respective one of a plurality of internal clock signals;
an external control signal input circuit for receiving an external control signal and generating an internal control signal;
and
an output control circuit for receiving the internal control signal and controlling the output of the internal clock signals, wherein the output control circuit includes:
a latch circuit connected to the external control signal input circuit and the first clock signal input circuit, wherein the latch circuit latches the internal control signal in response to a first internal clock signal generated by the first clock signal input circuit;
a first enable signal generating circuit connected to the latch circuit and the first clock signal input circuit, wherein the first enable signal generating circuit holds the latched internal control signal in response to the first internal clock signal and generates a first enable signal;
a second enable signal generating circuit connected to the latch circuit and the second clock signal input circuit, wherein the second enable signal generating circuit holds the latched internal control signal in response to the second internal clock signal and generates a second enable signal for selectively activating and deactivating the first and second clock signal input circuits;
a first gate circuit connected to the first enable signal generating circuit and the first clock signal input circuit, wherein the first gate circuit controls the output of the first internal clock signal in accordance with the first enable signal;
and
a second gate circuit connected to the second enable signal generating circuit and the second clock signal input circuit, wherein the second gate circuit controls the output of the second internal clock signal in accordance with the second enable signal.

7 more elements

A semiconductor integrated circuit comprising:

a first clock signal input buffer and a second clock signal input buffer for receiving first and second external clock signals, each having a different phase, and generating first and second internal clock signals, each having a different phase, respectively;
a power-down signal input buffer for receiving an external power-down signal and generating an internal power-down signal;
and
an output control circuit for receiving the internal power down signal from the power-down signal input buffer, wherein the output control circuit includes:
a latch circuit connected to the power-down signal input buffer and the first clock signal input buffer, wherein the latch circuit latches the internal power-down signal in response to the first internal clock signal;
a first enable signal generating circuit connected to the latch circuit and the first clock signal input buffer, wherein the first enable signal generating circuit holds the latched internal power-down signal in response to the first internal clock signal and generates a first enable signal;
a gate circuit connected to the first enable signal generating circuit and the first clock signal input buffer, wherein the gate circuit controls the output of the first internal clock signal in accordance with the first enable signal;
and
a second enable signal generating circuit connected to the first enable signal generating circuit and the second clock signal input buffer, wherein the second enable signal generating circuit holds the first enable signal in response to the first internal clock signal and generates a second enable signal for selectively activating and deactivating the second clock signal input buffer.

6 more elements

A semiconductor integrated circuit comprising:

a first clock signal input buffer and a second clock signal input buffer for receiving first and second external clock signals, each having a different phase, and generating first and second internal clock signals, each having a different phase, respectively;
a power-down signal input buffer for receiving an external power-down signal and generating an internal power-down signal;
and
an output control circuit for receiving the internal power down signal from the power-down signal input buffer, wherein the output control circuit includes:
a latch circuit connected to the power-down signal input buffer and the first clock signal input buffer, wherein the latch circuit latches the internal power-down signal in response to the first internal clock signal;
a first enable signal generating circuit connected to the first clock signal input buffer and the latch circuit, wherein the first enable signal generating circuit holds the latched internal power-down signal in response to the first internal clock signal to generate a first enable signal;
a second enable signal generating circuit connected to the latch circuit and the second clock signal input buffer, wherein the second enable signal generating circuit holds the latched internal power-down signal in response to the second internal clock signal to generate a second enable signal;
a first gate circuit connected to the first enable signal generating circuit and the first clock signal input buffer, wherein the first gate circuit controls the output of the first internal clock signal in accordance with the first enable signal;
a second gate circuit connected to the second enable signal generating circuit and the second clock signal input buffer, wherein the second gate circuit controls the output of the second internal clock signal in accordance with the second enable signal;
and
a third gate circuit connected to the latch circuit and the second enable signal generating circuit, wherein the third gate circuit receives the latched internal power-down signal and the second enable signal to provide the first and second clock signal input buffers with a third enable signal.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/385,007Filed 27 Aug 1999
Priority: JP 10-32936919 Nov 1998
Granted: 14 Aug 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
G11C 7/1072
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
H03K 5/2481
Using field effect transistors: with at least one differential stage