Phase modulated input/output circuit

Abstract

A circuit is designed with a delay circuit (300,301,500) coupled to receive a bias (256) and a reference signal (242). The delay circuit produces a series of phase signals (214). The phase signals are spaced apart in time in response to the bias. Each phase signal has a respective time after the reference signal. Each phase corresponds to logic states of a plurality of data signals. An encoder circuit (900,1100) is coupled to receive a first phase signal and a first plurality of data signals (212). The encoder circuit produces a first encoded data signal (220) at a time corresponding to the respective time of the first phase signal. A decoder circuit (600,800) is coupled to receive a second phase signal and a second encoded data signal (220) corresponding to the respective time of the second phase signal. The decoder circuit produces a second plurality of data signals (212) corresponding to the second phase signal.

Dependencies are inferred from the claim text.