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US 6,275,080 B1Granted
Enhanced single event upset immune latch circuit
AssigneeBAE SYSTEMS plc
InventorsHo G. Phan, Derwin L. Jallice, Bin Li
Life of this patent
Estimating the term…
Abstract
An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.
Claims22
An enhanced single event immune latch comprising:
- a first PMOS transistor and a first NMOS transistor coupled together at a first drain-source region of said first PMOS transistor and a first drain-source region of said first NMOS transistor;
- a first PMOS isolation transistor and a first NMOS isolation transistor coupled together at first source-drain regions of said first PMOS isolation transistor and said first NMOS isolation transistor, and coupled at a second drain-source region of said first PMOS isolation transistor to a second drain-source region of said first PMOS transistor and at a second drain-source region of said first NMOS isolation transistor to a second drain-source region of said first NMOS transistor, wherein a gate of said first PMOS isolation transistor is coupled to low voltage and a gate of said first NMOS isolation transistor is coupled to high voltage;
- a second PMOS transistor coupled at a gate to said second drain-source region of said first PMOS and to said second drain-source region of said first isolation PMOS, wherein said second PMOS transistor is coupled at a first drain-source region to VDD;
- a second NMOS transistor coupled at a gate to said second drain-source region of said first NMOS and to said second drain-source region of said first isolation NMOS, wherein said second NMOS transistor is coupled at a first drain-source region to GND;
- a second PMOS isolation transistor and a second NMOS isolation transistor coupled together at first source-drain regions of said second PMOS isolation transistor and said second NMOS isolation transistor, and coupled at a second drain-source region of said second PMOS isolation transistor to a second drain-source region of said second PMOS transistor and at a second drain-source-region of said second NMOS isolation transistor to a second drain-source region of said second NMOS transistor, wherein a gate of said second PMOS isolation transistor is coupled to low voltage and a gate of said second NMOS isolation transistor is coupled to high voltage;
- a feedback PMOS transistor coupled at a first drain-source region to said second drain-source region of said first PMOS transistor;
- a feedback NMOS transistor coupled at a first drain-source region to said second drain-source region of said first NMOS transistor;
- a third PMOS transistor coupled at a first drain-source region to a second drain-source region of said feedback PMOS transistor, and at a gate to said second drain-source region of said second PMOS isolation transistor, and at a second drain-source region to VDD;
- a third NMOS transistor coupled at a first drain-source region to a second drain-source region of said feedback NMOS transistor, and at a gate to said second drain-source region of said second NMOS isolation transistor, and at a second drain-source region to GND;
- a data input that is coupled to said first drain-source region of said first PMOS transistor and said first drain-source region of said first NMOS transistor;
- a clock coupled to a gate of said first NMOS transistor and a gate of said feedback PMOS transistor;
- and
- a complementary clock of said clock coupled to a gate of said first PMOS transistor and a gate of said feedback NMOS transistor.
10 more elements
A method for providing immunity using isolation transistors in an enhanced single event offset bi-stable circuit comprising the steps of:
- storing data in a register at a drain-source region of a first PMOS isolation transistor and at a drain-source region of a first NMOS isolation transistor, wherein said drain-source regions are logically equivalent;
- placing a drain-source region of a second PMOS isolation transistor and a drain-source region of a second NMOS isolation transistor in a logic state opposite that of said drain-source regions of said first PMOS isolation and said first NMOS isolation transistors, wherein said drain-source regions of said second PMOS isolation transistor and said second NMOS isolation transistors are also logically equivalent;
- writing the data into said register including setting a drain-source region of a PMOS feedback transistor at the same potential as said drain-source regions of said first PMOS isolation and said first NMOS isolation transistors;
- setting a drain-source region of an NMOS feedback transistor at a potential equal to the potential at the drain source region of the first NMOS isolation transistor;
- and
- avoiding upset or loss of data in said register during a single event upset (SEU) producing an energizing ion strike to said drain-source region of said first NMOS isolation transistor causing a sharp drop in potential of said drain-source region of said first NMOS isolation transistor, including using said first PMOS isolation transistor and said first NMOS isolation transistor to permit potential at said drain-source region of said first PMOS isolation transistor to be pulled down by only a small amount before the potential at said drain-source region of said first NMOS isolation transistor is restored.
3 more elements
A latch comprising:
- first, second, and third p-type transistors, each having an input and output;
- first, second, and third n-type transistors each having an input and output;
- a first p-type isolation device and a first n-type isolation device coupled between the outputs of the first p-type and first n-type transistors;
- a first feedback transistor coupling the output of the third p-type transistor to the input of the second p-type transistor;
- a second feedback transistor coupling the output of the third n-type transistor to the input of the second n-type transistor;
- and
- a second p-type isolation device and a second n-type isolation device coupled between the outputs of the second p-type and second n-type transistors.
4 more elements
A digital signal processor (DSP) comprising:
- a latch comprising,
- first, second, and third p-type transistors, each having an input and output;
- first, second, and third n-type transistors each having an input and output;
- a first p-type isolation device and a first n-type isolation device coupled between the outputs of the first p-type and first n-type transistors;
- a first feedback transistor coupling the output of the third p-type transistor to the input of the second p-type transistor;
- a second feedback transistor coupling the output of the third n-type transistor to the input of the second n-type transistor;
- and
- a second p-type isolation device and a second n-type isolation device coupled between the outputs of the second p-type and second n-type transistors.
5 more elements
A microprocessor comprising a register, said register comprising:
- first, second, and third p-type transistors, each having an input and output;
- first, second, and third n-type transistors each having an input and output;
- a first p-type isolation device and a first n-type isolation device coupled between the outputs of the first p-type and first n-type transistors;
- a first feedback transistor coupling the output of the third p-type transistor to the input of the second p-type transistor;
- a second feedback transistor coupling the output of the third n-type transistor to the input of the second n-type transistor;
- and
- a second p-type isolation device and a second n-type isolation device coupled between the outputs of the second p-type and second n-type transistors.
4 more elements
A method of operating a radiation hardened storage cell latch circuit comprising:
- suppressing a logic state change of the storage cell latch circuit that has a source-drain region coupled p-type isolation and n-type isolation transistors and p-type feedback and n-type feedback transistors in response to a particle hit on a circuit node of the latch circuit;
- recovering from a critical charge deposited on the circuit as a result of said particle hit on said circuit node;
- and
- isolating said node circuit by increasing source/drain impedance RC delay of transistors, thereby slowing feedback propagation through and allowing more time for recovery from the suppressing a state change step.
1 more element
Dependencies are inferred from the claim text.