Analog delay locked loop circuit
AssigneeHyundai Electronics Industries Co., Ltd.
InventorBoo Young Park
Life of this patent
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Abstract
An analog delay locked loop circuit includes: a phase detector detecting a phase difference between an external clock signal and an internal clock signal, a charge pump performing a pumping operation according to an output from the phase detector, a low pass filter filtering an output from the charge pump, and outputting a control voltage, a supply power selecting unit outputting a first supply power or a second supply power according to a supply power selecting signal, a voltage control delay unit receiving a supply power selected by the supply power selecting unit, and delaying the external clock signal for a predetermined time according to the control voltage from the low pass filter, and a driver amplifying an output from the voltage control delay unit, and generating the internal clock signal.
Claims23
An analog delay locked loop circuit comprising:
- a phase detector for detecting a phase difference between a first clock signal and a fed-back second clock signal;
- a charge pump for carrying out a pumping operation according to an output from the phase detector;
- a low pass filter for filtering an output from the charge pump, and for outputting a control voltage;
- a supply power selecting unit for outputting a first supply power or a second supply power in accordance with a supply power selecting signal;
- a voltage control delay unit for receiving a supply power selected in the supply power selecting unit, and for delaying the first clock signal in accordance with the control voltage from the low pass filter;
- and
- a driver for amplifying an output from the voltage control delay unit, and for generating the second clock signal.
An analog delay locked loop circuit comprises:
- a phase detector for detecting a phase difference between an external clock signal and an internal clock signal;
- a charge pump for carrying out a pumping operation according to an output from the phase detector;
- a low pass filter for filtering an output from the charge pump, and outputting a control voltage;
- a multiplexer for outputting one of first to third supply power in accordance with a supply power selecting signal;
- and
- a voltage control delay unit for receiving a supply power outputted from the multiplexer, and for delaying the external clock signal according to the control voltage from the low pass filter,
- wherein the internal clock signal is based on the delayed external clock signal from the voltage control delay unit.
An analog delay locked loop circuit comprising:
- a phase detector that detects a phase difference between a first clock signal and a fed-back second clock signal;
- a control unit that outputs a control voltage according to an output from the phase detector;
- a supply power selector that selectively outputs a first supply power that determines a first delay range and a second supply power that determines a second delay range responsive to a supply power selecting signal;
- a voltage control delay unit that receives a supply power selected in the supply power selecting unit and delays the first clock signal within a corresponding selected one of the first and second delay ranges in accordance with the control voltage from the low pass filter;
- and
- a driver that receives an output from the voltage control delay unit, and generates the second clock signal.
Dependencies are inferred from the claim text.