Combined phase comparator and charge pump circuit
AssigneeVelio Communications, Inc.
InventorsWilliam J. Dally, Ramin Farjad-Rad, Teva J. Stone, Xiaoying Yu, John W. Poulton
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Abstract
A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control the phase of one of the timing signals. The phase comparator and charge pump circuit can be included in a multiplier circuitry in which the phase of an input signal is directly compared to the phase of an edge of the multiplied signal.
Claims52
A phase comparator which compares the phase of an edge of a first timing signal and an edge of a second timing signal, comprising:
- first and second timing signal inputs;
- a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- combinational circuitry having an output which depends only on the state of its input, the combinational circuitry receiving the timing signals and the window signal and providing a phase comparison of the edges of the first and second timing signals as an output signal.
A phase comparator which compares the phase of an edge of a first timing signal and an edge of a second timing signal, comprising:
- first and second timing signal inputs;
- a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared, the window signal being true during the rising edges of the timing signals and false during the falling edges of the timing signals;
- and
- combinational circuitry receiving the timing signals and the window signal and providing a phase comparison of the edges of the first and second timing signals as an output signal.
A phase comparator which compares the phase of an edge of a first timing signal and an edge of a second timing signal, comprising:
- first and second timing signal inputs;
- a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- combinational circuitry receiving the timing signals and the window signal and providing a phase comparison of the edges of the first and second timing signals as an output signal, the timing signals and their complements being ANDed with the window signal.
A phase comparator which compares the phase of an edge of a first timing signal and an edge of a second timing signal, comprising:
- first and second timing signal inputs;
- a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- combinational circuitry receiving the timing signals and the window signal and providing a phase comparison of the edges of the first and second timing signals as an output signal, the output signal being generated by sourcing current to the output when the first timing signal leads a second timing signal and draining current from the output when the first timing signal lags the second timing signal.
A phase comparator which compares the phase of an edge of a first timing signal and an edge of a second timing signal, comprising:
- first and second timing signal inputs;
- a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- combinational circuitry receiving the timing signals and the window signal and providing a phase comparison of the edges of the first and second timing signals as an output signal, the phase comparison being made on both the rising edges and the falling edges of the first and second timing signals.
A phase comparator in combination with a frequency generating circuit which generates an output signal at a frequency rate that is a multiple of an input frequency, the phase comparator providing a phase comparison of an edge of the input signal and an edge of the output signal and controlling the frequency generating circuit based on the comparison, the phase comparator comprising:
- a window signal that is true during said edge of the input signal and said edge of the output signal to be compared;
- and
- combinational circuitry receiving the input signal, the output signal and the window signal and providing a phase comparison of the edges of the input signal and the output signal.
A method of comparing the phase of an edge of a first timing signal and an edge of a second timing signal comprising:
- generating a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- in combinational circuitry, having an output which depends only on the state of its input, receiving the timing signals and the window signal and providing a phase comparison of the edges of the first and second timing signals as an output signal.
The method of comparing the phase of an edge of a first timing signal and an edge of a second timing signal comprising:
- generating a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared, the window signal being true during the rising edges of the timing signals and false during the falling edges of the timing signals;
- and
- in combinational circuitry receiving the timing signals and the window signal, providing a phase comparison of the edges of the first and second timing signals as an output signal.
A method of comparing the phase of an edge of a first timing signal and an edge of a second timing signal comprising:
- generating a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- in combinational circuitry receiving the timing signals and the window signal, providing a phase comparison of the edges of the first and second timing signals as an output signal, the timing signals and their complements being ANDed with the window signal.
A method as claimed in 32 wherein the output signal comprises an up signal and a down signal, the up signal being derived by ANDing the window signal with the first timing signal and the complement of the second timing signal and the down signal being derived by ANDing the window signal with the second timing signal and the complement of the first timing signal.
A method of comparing the phase of an edge of a first timing signal and an edge of a second timing signal comprising:
- generating a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- in combinational circuitry receiving the timing signals and the window signal, providing a phase comparison of the edges of the first and second timing signals as an output signal, the output signal being generated by sourcing current to the output when the first timing signal leads a second timing signal and draining current from the output when the first timing signal lags the second timing signal.
A method as claimed in 42 wherein the first branch is a pull-up branch.
A method as claimed in 42 wherein the first branch includes a first switching device gated by the window signal, a second switching device gated by the first timing signal and a third switching device gated by a complement of the second timing signal.
A method of comparing the phase of an edge of a first timing signal and an edge of a second timing signal comprising:
- generating a window signal that is true during said edge of the first timing signal and said edge of the second timing signal to be compared;
- and
- in combinational circuitry receiving the timing signals and the window signal, providing a phase comparison of the edges of the first and second timing signals as an output signal, a phase comparison being made on both the rising edges and the falling edges of the first and second timing signals.
A method of generating an output signal comprising:
- generating a window signal that is true during an edge of an input signal and an edge of the output signal;
- in combinational circuitry receiving the input signal, output signal and the window signal, providing a phase comparison of the edges of the input signal and the output signal;
- and
- generating an output signal at a frequency that is a multiple of an input frequency and controlling the frequency of the output signal based on the phase comparison of the edge of the input signal and the edge of the output signal.
Dependencies are inferred from the claim text.