Integrated circuit having a high speed clock input buffer

A buffer circuit, comprising:

• a first inverter, comprising:
• a first P-channel transistor having a first current electrode coupled to a first power supply voltage t for receiving a first power supply voltage, a second current electrode for forming an output terminal of the first inverter, and a control electrode for receiving an input signal;
• and
• a fist N-channel transistor have a first current electrode coupled to the second current electrode of the first P-channel transistor, a second current electode coupled to a ground terminal, and a control electrode coupled to the control electrode of the first P-channel transistor;
• a level shifter comprising;
• a second P-channel transistor having a first current electrode coupled to a second power supply voltage terminal for receiving a second power supply voltage that is lower than he first power supply voltage, a second current electrode, and a control electrode;
• a third P-channel transistor having a first current electrode coupled to the second power supply voltage terminal, a second current electrode coupled to the control electrode of the second P-channel transistor, and a control electrode coupled to the second current electrode of the second P-channel transistor;
• a second N-channel transistor having a first current electrode coupled to the second current electode of the second P-channel transistor, a second current electrode coupled to the ground terminal, and a control electrode coupled to the output terminal of the first inverter;
• and
• a third N-chapel transistor having a first current electrode coupled to the second current electrode of the third P-channel transistor, a second current electrode, and a control electode coupled to receive the input signal;
• a second inverter having series-connected P-channel and N-channel transistors coupled between the second power supply voltage terminal and the ground terminal, the P-channel and N-channel transistors having control electrodes coupled to the second current electrode of the second P-channel transistor, and an output terminal formed between the series-connected P-channel and N-channel transistors for providing a buffered input signal;
• a third inverter coupled to the output terminal of the second inverter and an output for providing a logical complement of the buffered input signal;
• and
• a delay circuit having an input for receiving the input signal at a first logic state, the delay circuit for causing the level shifted output signal to transition to a second logic state that is different tan the first logic state, wherein the level shifted input signal has a duration and duty cycle that is independent of a duration and duty cycle of the input signal.

An input buffer circuit, comprising:

• a first stage having an input terminal for receiving an input signal, and an output terminal, the first stage coupled to a first power supply voltage terminal for receiving a first power supply voltage;
• a level shifter having a pair of cross-coupled P-channel transistors coupled to a second power supply voltage teal for receiving a second power supply voltage, the second power supply voltage being different than the first power supply voltage, the cross-coupled P-channel transistors being coupled to first current electrodes of first and second N-channel transistors, and where a gate of the first N-channel transistor is coupled to the output terminal of the input stage and a gate of the second N-channel transistor is coupled to receive the input signal, the level shifter providing a level shifted output signal at the first current electrode of the second N-channel transistor;
• and
• a delay circuit, comprising:
• a delay element having and input terminal for receiving the input signal, and an output terminal;
• a first P-channel transistor having a first current electrode coupled to the second power supply voltage terminal, a second current electrode coupled to the first current electrode of the second N-channel transistor, and a gate electrode coupled to the output terminal of the delay element;
• and
• a third N-channel transistor having a first current electrode coupled to a second current electrode of the second N-channel transistor, a second current electrode coupled to a ground terminal, and a control electrode coupled to the output terminal of the delay element, wherein the delay circuit for receiving the input signal at a first logic state, the delay circuit for causing be level shifted output signal to transition to a second logic state that is different than the first logic state, wherein the level shifted input signal has a duration and duty cycle tat is independent of a duration and duty cycle of the input signal.