Programmable logic integrated circuit architecture incorporating a lonely register

A programmable logic device comprising:

• a first plurality of conductors, extending along a first dimension of a two-dimensional array;
• a second plurality of conductors, extending along a second dimension of the two-dimensional array, wherein the second plurality of conductors is programmably coupled to the first plurality of conductors;
• and
• a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors, wherein a logic array block comprises:
• a first multiplexer coupled through an output buffer to an I/O pad of the programmable logic device;
• a plurality of logic modules coupled to the first multiplexer configured to implement combinatorial logic;
• a second multiplexer coupled to the plurality of logic modules;
• a register comprising a first output coupled to the first multiplexer and having a data input coupled to the second multiplexer, wherein one of the plurality of logic modules may be programmably coupled to the register while others of the plurality of logic modules are programmably coupled to the first multiplexer, bypassing the register;
• and
• a third multiplexer coupled to the plurality of logic modules and a second output of the register.

A logic element for a programmable logic device comprising:

• a first multiplexer coupled through an output buffer to an I/O pad of the programmable logic device;
• a second multiplexer programmably coupled to a global interconnect of the programmable logic device;
• a third multiplexer;
• a plurality of logic modules, coupled to the first multiplexer, second multiplexer, and third multiplexer, configured to implement combinatorial logic;
• and
• a register coupled to the first multiplexer, second multiplexer, and the plurality of logic modules using the third multiplexer, wherein one of the plurality of logic modules may be programmably coupled to the register while others of the plurality of logic modules are programmably coupled to the first multiplexer, bypassing the register, wherein the third multiplexer is coupled to a data input of the register.

A logic element for a programmable integrated circuit comprising:

• a plurality of combinatorial outputs from logic modules programmably configurable to perform logic;
• a register comprising a data input and a data output;
• a first multiplexer comprising a first input coupled to the data output and a second input coupled to the plurality of combinatorial outputs;
• and
• a second multiplexer to programmably couple the plurality of combinatorial outputs to the data input to the register,
• wherein the logic modules comprise programmable AND gates.

A logic element for a programmable integrated circuit comprising:

• a plurality of combinatorial outputs from logic modules programmably configurable to perform logic;
• a register comprising a data input and a data output;
• a first multiplexer comprising a first input coupled to the data output, a second input coupled to the plurality of combinatorial outputs, and an output coupled through an output buffer to an I/O pad of the programmable integrated circuit;
• and
• a second multiplexer to programmably couple the plurality of combinatorial outputs to the data input to the register.

A logic element for a programmable integrated circuit comprising:

• a plurality of combinatorial outputs from logic modules programmably configurable to perform logic;
• a register comprising a data input and a data output;
• a multiplexer comprising a first input coupled to the data output and a second input coupled to the plurality of combinatorial outputs;
• and
• a plurality of multiplexers to programmably couple the plurality of combinatorial outputs or an I/O pad to the data input to the register.

A logic element for a programmable integrated circuit comprising:

• a plurality of combinatorial outputs from logic modules programmably configurable to perform logic;
• a register comprising a data input and a data output;
• a multiplexer comprising a first input coupled to the data output and a second input coupled to the plurality of combinatorial outputs;
• and
• a plurality of multiplexers to programmably couple the plurality of combinatorial outputs or the data output to the data input to the register.